2007 IEEE International Conf. On Application-Specific Systems, Architectures and Processors (ASAP) 2007
DOI: 10.1109/asap.2007.4429951
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Parallelizing HMMER for Hardware Acceleration on FPGAs

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Cited by 26 publications
(22 citation statements)
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References 31 publications
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“…As the Viterbi algorithm has been used in many topics, such as pairwise alignments, multiple sequence alignment and gene prediction, there is much research focusing on the acceleration of the Viterbi algorithm [10][11] [12]. The acceleration of the Viterbi algorithm commonly utilizes a log-transformation of the original equations, which transform floating-point multiplication operations into floating-point addition operations.…”
Section: Related Workmentioning
confidence: 99%
“…As the Viterbi algorithm has been used in many topics, such as pairwise alignments, multiple sequence alignment and gene prediction, there is much research focusing on the acceleration of the Viterbi algorithm [10][11] [12]. The acceleration of the Viterbi algorithm commonly utilizes a log-transformation of the original equations, which transform floating-point multiplication operations into floating-point addition operations.…”
Section: Related Workmentioning
confidence: 99%
“…Automatic generation of systolic arrays to implement pipelined evaluation of uniform and affine recurrence equations 9 have been studied and found to give significant speedup for many problems. Numerous accelerators for HMMER and Smith-Waterman exist for which the evaluation time is decreased via a combination of architectural improvements, 8,[10][11][12] data path redesign, [13][14][15][16][17][18] and heuristics. 19,20 To our best knowledge, none of the accelerators mentioned above do rely exclusively on algorithmic improvement techniques as we do.…”
Section: Discussion and Related Workmentioning
confidence: 99%
“…They get a 700 MCUPS on XC3S1500, but the emission storage is not introduced. Derrien, et al [13] have the same motivation with us in that they want to accelerate an individual query, but they work out their problem in a more complex way. They get a 330 MCUPS to 660MCUPS performance.…”
Section: Related Workmentioning
confidence: 99%
“…Many solutions [1] [11] [15] are based on the simplified HMM without a rare feedback loop in HMM, while other implementations accelerates full Plan7 HMM [14] [13]. FPGA and MPI are combined into an MPI-HMMER-Boost to achieve a better speedup [8].…”
Section: Introductionmentioning
confidence: 99%