Parallelizing Data Processing on FPGAs with Shifter Lists

Abstract

Parallelism is currently seen as a mechanism to minimize the impact of the power and heat dissipation problems encountered in modern hardware. Data parallelism-based on partitioning the data-and pipeline parallelism-based on partitioning the computation-are the two main approaches to leverage parallelism on a wide range of hardware platforms.Unfortunately, not all data processing problems are susceptible to either of those strategies. An example is the skyline operator [Börzsönyi et al. 2001], which computes the set of Pareto-optimal points within a multidimensional dataset. Existing approaches to parallelize the skyline operator are based on data parallelism. As a result, they suffer from a high overhead when merging intermediate results because of the lack of a global view of the problem inherent to partitioning the input data.In this article, we show how to combine pipeline with data parallelism on a Field-Programmable Gate Array (FPGA) for a more efficient utilization of the available hardware parallelism. As we show in our experiments, skyline computation using our proposed technique scales linearly with the number of processing elements, and the performance we achieve on a rather small FPGA is comparable to that of a 64-core high-end server running a state-of-the-art data parallel implementation of skyline [Park et al. 2009].The proposed approach to parallelize the skyline operator can be generalized to a wider range of data processing problems. We demonstrate this through a novel, highly parallel data structure, a shifter list, that can be efficiently implemented on an FPGA. The resulting template is easy to parametrize to implement a variety of computationally intensive operators such as frequent items, n-closest pairs, or K-means.

MEMOCODE 2015 design contest: Continuous skyline computation

“…For example, [14] shows how the dominance operator can be computed in a branch-free manner to make it suitable for GPU and [15] details a partitioning scheme providing further improvements. Meanwhile, [16] presents a highly scalable parallel FPGA technique for computing the skyline; the authors later generalized this idea into a new computational structure called a shifter list [17].…”

The New Hardware Development Trend and the Challenges in Data Management and Analysis

“…Academics and industry are beginning to explore some new ways to accelerate the performance of data processing through software/hardware co-design. Instructionlevel optimization [16], coprocessor query optimization [17,18], hardware customization [19], workload hardware migration [20], increasing hardware-level parallelism [21], hardware-level operators [22], and so on are used to provide hardware-level performance optimization. However, the differences between the new processor and x86 processor fundamentally change the assumptions of traditional database software design on hardware.…”