Parallelism in analog and digital PRML magnetic disk read channel equalizers

Uehara, G.T.; Gray, P.R.

doi:10.1109/20.364803

Cited by 11 publications

(2 citation statements)

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“…It can be seen that the output harmonic distortion increases with the input signal amplitude. Furthermore, the third harmonic distortion goes up at a faster rate than the second harmonic distortion, as predicted by (2) and (3). To check the dependence of harmonic distortion on the input magnitude, measurements of the second and third harmonic distortion are plotted for different input values in Fig.…”

Section: A Distortionmentioning

confidence: 88%

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A low-power 170-MHz discrete-time analog FIR filter

Wang¹,

Spencer²

1998

IEEE J. Solid-State Circuits

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A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2-m CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC's) with 6-b resolution. Index Terms-Analog FIR filter, circular buffer architecture, discrete-time, fixed pattern noise, low power CMOS circuits. I. INTRODUCTION M ANY applications require high-speed low-power equalizers with moderate resolution. Analog equalizers are almost ideally suited for these applications since they can typically provide the required performance with less power and area than their digital counterparts. As an example, modern magnetic storage channels, which usually use partial-response maximum-likelihood (PRML) detection, require a linear equalizer to shape the channel response [1]-[4]. The desired channel response is described by the equivalent discrete-time transfer function for the sampled channel. The most common polynomials for magnetic recording are the so-called extended partial-response (PR) polynomials given by (1) This paper presents a discrete-time analog implementation of a 9-tap finite impulse response (FIR) equalizer suitable for use in a magnetic storage read channel. A circular buffer architecture is used in this design [5], [6], [13]. Compared to a direct-form or transposed FIR filter, the circular buffer architecture can achieve higher-speed operation since the trackand-hold (T/H) cells can have more than one sample period for acquisition and/or hold settling. In previous work using the same structure [6], two time-interleaved parallel transconductors were used for a 9-tap filter to achieve a speed of 200 MHz using a 0.6m CMOS process with a total power dissipation of 507 mW. The disadvantages of that implementation are: 1) the large power dissipation and 2) due to the interleaved structure, the architecture is only suitable for interleaved Manuscript

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Section: A Distortionmentioning

confidence: 88%

“…The second is that the relation cannot be treated as linear for large signal analysis, which mainly contributes to third harmonic distortion. The details are shown in the Appendix and the two formulas for the harmonic distortions are HD (2) and HD…”

Section: A Multiplicationmentioning

confidence: 99%