A low-power 170-MHz discrete-time analog FIR filter

Abstract

A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2-m CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC's) with 6-b resolution. Index Terms-Analog FIR filter, circular buffer architecture, discrete-time, fixed pattern noise, low power CMOS circuits. I. INTRODUCTION M ANY applications require high-speed low-power equalizers with moderate resolution. Analog equalizers are almost ideally suited for these applications since they can typically provide the required performance with less power and area than their digital counterparts. As an example, modern magnetic storage channels, which usually use partial-response maximum-likelihood (PRML) detection, require a linear equalizer to shape the channel response [1]-[4]. The desired channel response is described by the equivalent discrete-time transfer function for the sampled channel. The most common polynomials for magnetic recording are the so-called extended partial-response (PR) polynomials given by (1) This paper presents a discrete-time analog implementation of a 9-tap finite impulse response (FIR) equalizer suitable for use in a magnetic storage read channel. A circular buffer architecture is used in this design [5], [6], [13]. Compared to a direct-form or transposed FIR filter, the circular buffer architecture can achieve higher-speed operation since the trackand-hold (T/H) cells can have more than one sample period for acquisition and/or hold settling. In previous work using the same structure [6], two time-interleaved parallel transconductors were used for a 9-tap filter to achieve a speed of 200 MHz using a 0.6m CMOS process with a total power dissipation of 507 mW. The disadvantages of that implementation are: 1) the large power dissipation and 2) due to the interleaved structure, the architecture is only suitable for interleaved Manuscript

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

“…The design method commonly adopted for SDFIR DAC, is to use a standard digital FIR filter design algorithms (e.g. Parks-McClellan algorithm [90]), and choose a practical numerical resolution for the FIR coefficients [116,55,122,125,18,34,66]. The design of linear-phase FIR filters with fractional coefficients are widely discussed in the literature [96,123].…”

“…Semi-digital FIR filters or sometimes called analog FIR filters, are used as frequency selective filters as well as converting from digital domain to analog domain since it uses analog multipliers as filter taps. The analog multipliers are implemented by means of current sources, in conventional SDFIR filters, if the output of the Σ∆ modulator quantizer is a single bit [116,122,18,34,87,105,124,46,109]. In fact each tap is one-bit DAC and they are weighted according to the filter coefficients.…”

“…5.1, to an interpolating stage, digital Σ∆ modulator and a semi-digital finite-impulse response (FIR) filter. Semi-digital FIR digital-to-analog converters (SDFIR DAC), used as filters and data converters, are implemented as switched-capacitor network or in current-steering architectures, and reported previously in [116,122,18,34,87,105,124,48,47,46]. In this configuration, N -bit baseband data is up-sampled and filtered through the interpolator and then applied to the digital Σ∆ modulator.…”

Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

“…Semi-digital FIR filters or sometimes called analog FIR filters, are used as frequency selective filters as well as converting from digital domain to analog domain since it uses analog multipliers as filter taps. The analog multipliers are implemented by means of current sources, in conventional SDFIR filters, if the output of the Σ∆ modulator quantizer is a single bit [15,16,17,18,19,20,21,12,22]. In fact each tap is one-bit DAC and they are weighted according to the filter coefficients.…”

Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics

“…The design method commonly adopted for SDFIR DAC, is to use a standard digital FIR filter design algorithms (e.g. Parks-McClellan algorithm [17]), and choose a practical numerical resolution for the FIR coefficients [2,4,9,11,22,23,26]. The design of linear-phase FIR filters with fractional coefficients are widely discussed in the literature [20,24].…”