Parallel simulation of chip-multiprocessor architectures

Chidester, Matthew C.; George, Alan

doi:10.1145/643114.643116

Cited by 51 publications

(23 citation statements)

References 23 publications

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“…The projects most closely related to Graphite are parallel simulators of parallel target architectures including: SimFlex [33], GEMS [24], COTSon [26], BigSim [36], FastMP [19], SlackSim [9], Wisconsin Wind Tunnel (WWT) [29], Wisconsin Wind Tunnel II (WWT II) [27], and those described by Chidester and George [10], and Penry et al [28].…”

Section: Related Workmentioning

confidence: 99%

Graphite: A distributed parallel simulator for multicores

Miller

Kasture

Kurian

et al. 2010

HPCA - 16 2010 the Sixteenth International Symposium on High-Performance Computer Architecture

351

227

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This paper introduces the open-source Graphite distributed parallel multicore simulator infrastructure. Graphite is designed from the ground up for exploration of future multicore processors containing dozens, hundreds, or even thousands of cores. It provides high performance for fast design space exploration and software development for future processors. Several techniques are used to achieve this performance including: direct execution, multi-machine distribution, analytical modeling, and lax synchronization. Graphite is capable of accelerating simulations by leveraging several machines. It can distribute simulation of an off-the-shelf threaded application across a cluster of commodity Linux machines with no modification to the source code. It does this by providing a single, shared address space and consistent single-process image across machines. Graphite is designed to be a simulation framework, allowing different component models to be easily replaced to either model different architectures or tradeoff accuracy for performance.We evaluate Graphite from a number of perspectives and demonstrate that it can simulate target architectures containing over 1000 cores on ten 8-core servers. Performance scales well as more machines are added with near linear speedup in many cases. Simulation slowdown is as low as 41× versus native execution for some applications.The Graphite infrastructure and existing models will be released as open-source software to allow the community to simulate their own architectures and extend and improve the framework.

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Section: Related Workmentioning

confidence: 99%

Graphite: A distributed parallel simulator for multicores

Miller

Kasture

Kurian

et al. 2010

HPCA - 16 2010 the Sixteenth International Symposium on High-Performance Computer Architecture

351

227

View full text Add to dashboard Cite

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“…The barrier serves three purposes: 1. Limit the skew between simulated cores: Barriers are the simplest and most common approach to bound the skew between cores [11,33]. While Graphite uses peer-to-peer synchronization to limit skew [27], this is only advantageous for simulations spread across loosely coupled clusters, where synchronization is much more expensive.…”

Section: Bound Phasementioning

confidence: 99%

ZSim

Sánchez

Kozyrakis

2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

315

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Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequential simulation even slower. Existing parallel simulation techniques either scale poorly due to excessive synchronization, or sacrifice accuracy by allowing event reordering and using simplistic contention models. As a result, most researchers use sequential simulators and model small-scale systems with 16-32 cores. With 100-core chips already available, developing simulators that scale to thousands of cores is crucial.We present three novel techniques that, together, make thousand-core simulation practical. First, we speed up detailed core models (including OOO cores) with instructiondriven timing models that leverage dynamic binary translation. Second, we introduce bound-weave, a two-phase parallelization technique that scales parallel simulation on multicore hosts efficiently with minimal loss of accuracy. Third, we implement lightweight user-level virtualization to support complex workloads, including multiprogrammed, client-server, and managed-runtime applications, without the need for full-system simulation, sidestepping the lack of scalable OSs and ISAs that support thousands of cores.We use these techniques to build zsim, a fast, scalable, and accurate simulator. On a 16-core host, zsim models a 1024-core chip at speeds of up to 1,500 MIPS using simple cores and up to 300 MIPS using detailed OOO cores, 2-3 orders of magnitude faster than existing parallel simulators. Simulator performance scales well with both the number of modeled cores and the number of host cores. We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.

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“…SIMFLEX [19], GEMS [20], COTSON [21], BIGSIM [22], FASTMP [23], SLACKSIM [24], PCASIM [25], Wisconsin Wind Tunnel (WWT) [26], Wisconsin Wind Tunnel II (WWT II) [27], and those described by Chidester and George [28], and Penry et al [29]. SIMFLEX and GEMS both use an off-theshelf sequential emulator (SIMICS) for functional modeling plus their own models for memory systems and core interactions.…”

Section: A Software Based Multi-core Simulation Approachesmentioning

confidence: 99%

Scalable multi-core simulation using parallel dynamic binary translation

Almer

Böhm

Koch

et al. 2011

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (ISS) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (JIT) dynamic binary translation (DBT). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (ISA). We have evaluated our parallel simulation methodology against the industry standard SPLASH-2 and EEMBC MULTIBENCH benchmarks and demonstrate simulation speeds up to 25,307 MIPS on a 32-core x86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead.

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Parallel simulation of chip-multiprocessor architectures

Cited by 51 publications

References 23 publications

Graphite: A distributed parallel simulator for multicores

Graphite: A distributed parallel simulator for multicores

ZSim

Scalable multi-core simulation using parallel dynamic binary translation

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