2016 XIX IEEE International Conference on Soft Computing and Measurements (SCM) 2016
DOI: 10.1109/scm.2016.7519731
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Parallel-pipeline implementation of digital signal processing techniques based on modular codes

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Cited by 6 publications
(6 citation statements)
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“…The block diagram of the proposed converting device is provided in Figure 2 The developed algorithm provides the residue formation for three modular cycles of the interfacing device. Thus, we can conclude that the developed conversion method provides significantly better performance than the existing conversion methods considered in [10].…”
mentioning
confidence: 78%
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“…The block diagram of the proposed converting device is provided in Figure 2 The developed algorithm provides the residue formation for three modular cycles of the interfacing device. Thus, we can conclude that the developed conversion method provides significantly better performance than the existing conversion methods considered in [10].…”
mentioning
confidence: 78%
“…Such systems are best suited for parallel computing. One of the most fruitful research areas here is the algebra of finite field, which provides an impressive level of internal parallelism [10] to the DSP systems.…”
Section: Introductionmentioning
confidence: 99%
“…After determining these parameters from Appendices 1 and 2, the most promising RNS moduli sets are these with the lowest possible β. These results can be used for building effective parallel computational systems [15] based on computers with parallel structure like FPGA and GPU [16,17]. The basic idea of a hardware implementation is that an algorithm (division, sign detection, comparison of numbers, reverse conversion) based on a diagonal function requires division by SQ.…”
Section: Balance Metric For Building Effective Computational Systemsmentioning
confidence: 99%
“…The comparative evaluation was carried out for the algorithm of the non-recursive filter implemented in the algebra of the finite field under the modular (tabular) execution of its basic operation. The basic operation time was selected as 2 ns (the time of reading data from the fast-acting memory device was 0.1-4 ns [16]), while the output sample was calculated in parallel pipeline mode, i.e., in one clock cycle of the processor.…”
Section: Of 14mentioning
confidence: 99%