Optimization of the FIR Filter Structure in Finite Residue Field Algebra

Kaplun, Dmitry; Butusov, Denis N.; Ostrovskii, Valerii Y.; Veligosha, A. V.; Gulvanskii, Vyacheslav V.

doi:10.3390/electronics7120372

Cited by 13 publications

(19 citation statements)

References 18 publications

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“…All these attractive features increase interest to RNS in the areas where large amounts of computation are needed. The applications of RNS are digital signal processing [2][3][4], cryptography [5][6][7], digital image processing [8], cloud computing [9], Internet of Things [10] and others. In [11], the authors propose a technique to estimate real-valued numbers by means of the Chinese remainder theorem (CRT), employing for this goal a Kroenecker based M-Estimation, to improve robustness.…”

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confidence: 99%

Construction of Residue Number System Using Hardware Efficient Diagonal Function

et al. 2019

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The residue number system (RNS) is a non-positional number system that allows one to perform addition and multiplication operations fast and in parallel. However, because the RNS is a non-positional number system, magnitude comparison of numbers in RNS form is impossible, so a division operation and an operation of reverse conversion into a positional form containing magnitude comparison operations are impossible too. Therefore, RNS has disadvantages in that some operations in RNS, such as reverse conversion into positional form, magnitude comparison, and division of numbers are problematic. One of the approaches to solve this problem is using the diagonal function (DF). In this paper, we propose a method of RNS construction with a convenient form of DF, which leads to the calculations modulo 2 n , 2 n − 1 or 2 n + 1 and allows us to design efficient hardware implementations. We constructed a hardware simulation of magnitude comparison and reverse conversion into a positional form using RNS with different moduli sets constructed by our proposed method, and used different approaches to perform magnitude comparison and reverse conversion: DF, Chinese remainder theorem (CRT) and CRT with fractional values (CRTf). Hardware modeling was performed on Xilinx Artix 7 xc7a200tfbg484-2 in Vivado 2016.3 and the strategy of synthesis was highly area optimized. The hardware simulation of magnitude comparison shows that, for three moduli, the proposed method allows us to reduce hardware resources by 5.98-49.72% in comparison with known methods. For the four moduli, the proposed method reduces delay by 4.92-21.95% and hardware costs by twice as much by comparison to known methods. A comparison of simulation results from the proposed moduli sets and balanced moduli sets shows that the use of these proposed moduli sets allows up to twice the reduction in circuit delay, although, in several cases, it requires more hardware resources than balanced moduli sets. such as field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). All these attractive features increase interest to RNS in the areas where large amounts of computation are needed. The applications of RNS are digital signal processing [2][3][4], cryptography [5][6][7], digital image processing [8], cloud computing [9], Internet of Things [10] and others. In [11], the authors propose a technique to estimate real-valued numbers by means of the Chinese remainder theorem (CRT), employing for this goal a Kroenecker based M-Estimation, to improve robustness. A new method based on the Chinese remainder theorem (CRT) is proposed for absolute position computation in [12]. This has advantages in terms of hardware and flexibility because it does not use memory. The authors of [13] offer to use RNS to improve the performance of the convolutional neural network developed for pattern recognition tasks. Reference [14] describes the method of construction for finite impulse response filers using RNS.However, the limitations of RNS include some operations such a...

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Construction of Residue Number System Using Hardware Efficient Diagonal Function

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“…Hardware simulation performed on FPGA Artix xc7a200tffg1156-3 in Xilinx Vivado 18.3 using VHDL hardware description language. The goal of the simulation was to compare the technical characteristics of the FIR DF implemented using known architectures in PNS [30] and in RNS [11,14] with the FIR DF using the proposed architecture in RNS with different moduli sets. Table V shows results of hardware simulation of 15th order FIR DF with different bit width.…”

Section: Hardware Simulation Of Digital Filters In the Residue Numentioning

confidence: 99%

“…The proposed method with 5modulus RNS allows to increase the frequency of the 15th order FIR DF by 2.0-4.2 times and reduce the hardware costs for its implementation by 1.1-2.6 times, with increasing power consumption by 7% -33% compared to the known method [30] based on PNS. Comparison with the known method [11] based on RNS with 5 moduli showed that proposed method allows to increase the frequency of the 15th order FIR DF by 1.6-4.4 times and reduce hardware costs for its implementation by 1.8-2.5 times with increasing power consumption by 11% -41%. The results of hardware simulation presented in Table VI show that use the proposed method of 3-modulus RNS allows to increase the frequency of FIR DF with = 16 by 1.9-2.2 times and reducing hardware costs for its implementation by 10% -44% with increasing power consumption by 6% -17% compared to the known method [30] based on PNS.…”

Section: Hardware Simulation Of Digital Filters In the Residue Numentioning

confidence: 99%

“…The authors propose a design methodology that provides automation of the design process for energy-efficient implementations of digital filters. Authors of the paper [11] propose a FIR DF architecture using RNS arithmetic, which allows reducing hardware costs compared to traditional FIR DF architecture. This approach uses suboptimal architectures based on hardware expensive RNS moduli of arbitrary form.…”

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High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

et al. 2020

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“…This fact follows from numerous publications dedicated to RNS usage in digital signal processing, image processing, antinoise coding, cryptographic systems, quantum automata, neurocomputers, systems with the massive parallelism of operations, cloud computing, DNA computing, etc. [1][2][3][4][5][6][7][8][9][10][11][12][13].…”

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A High-Speed Division Algorithm for Modular Numbers Based on the Chinese Remainder Theorem with Fractions and Its Hardware Implementation

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In this paper, a new simplified iterative division algorithm for modular numbers that is optimized on the basis of the Chinese remainder theorem (CRT) with fractions is developed. It requires less computational resources than the CRT with integers and mixed radix number systems (MRNS). The main idea of the algorithm is (a) to transform the residual representation of the dividend and divisor into a weighted fixed-point code and (b) to find the higher power of 2 in the divisor written in a residue number system (RNS). This information is acquired using the CRT with fractions: higher power is defined by the number of zeros standing before the first significant digit. All intermediate calculations of the algorithm involve the operations of right shift and subtraction, which explains its good performance. Due to the abovementioned techniques, the algorithm has higher speed and consumes less computational resources, thereby being more appropriate for the multidigit division of modular numbers than the algorithms described earlier. The new algorithm suggested in this paper has O (log2 Q) iterations, where Q is the quotient. For multidigit numbers, its modular division complexity is Q(N), where N denotes the number of bits in a certain fraction required to restore the number by remainders. Since the number N is written in a weighed system, the subtraction-based comparison runs very fast. Hence, this algorithm might be the best currently available.

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Optimization of the FIR Filter Structure in Finite Residue Field Algebra

Cited by 13 publications

References 18 publications

Construction of Residue Number System Using Hardware Efficient Diagonal Function

Construction of Residue Number System Using Hardware Efficient Diagonal Function

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

A High-Speed Division Algorithm for Modular Numbers Based on the Chinese Remainder Theorem with Fractions and Its Hardware Implementation

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