Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking

Abstract

This paper presents an improved reversible contrast mapping (RCM) algorithm for reversible invisible watermarking (RIW) in both software and hardware platforms. Based on well-known parameters for RIW like distortion, embedding bit rate, payload size and data hiding capacity, an efficient embedding bit rate control based contrast mapping (EBCRCM) algorithm is proposed. An adaptive linear contrast mapping on pixel intensity value is asserted with RCM that controls the embedding bit rate without changing the embedding capacity to maintain distortion. Xilinx system generator (XSG) and VIVADO tool construct the novel VLSI architecture that needs 173.362 ns latency for 100 MHz clock with throughput 46.146 Mbps and 5.8 ns critical path for single cycle of embedding process. The proposed algorithm is verified in MATLAB tool based software platform by taking different types of multimedia data like gray-scale images, color images and video signals. Implementation of low hardware resources based VLSI architecture through zed-board in real time field programmable gate array (FPGA) platform confirms the capability of high speed, low cost and real-time use. 100% agreement is observed from software simulations and hardware platforms.INDEX TERMS Reversible image watermarking, reversible contrast mapping, Xilinx system generator, FPGA.

Digital Steganography and Watermarking for Digital Images: A Review of Current Research Directions

“…However, in some cases we are talking about the reversible embedding of digital watermarks. For example, an improved reversible contrast mapping algorithm for reversible invisible watermarking is proposed in [57]. The watermark is fragile and is embedded into the spatial domain of the image.…”