Parallel hardware implementation of data hiding scheme for quality access control of grayscale image based on FPGA

Phadikar, Amit; Mandal, Himadri; Chiu, Tien‐Lung

doi:10.1007/s11045-019-00650-x

Cited by 5 publications

(2 citation statements)

References 28 publications

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“…The operating frequency was 1GHz, and the system could be reconfigured to implement several algorithms using the same hardware. In [23]. In [24] architecture was conducted to optimize parallel processing and implement this architecture on FPGA.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Mohammed¹,

Amir²,

Salih³

et al. 2022

IJACSA

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Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quadengine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image's part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing.

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Mohammed¹,

Amir²,

Salih³

et al. 2022

IJACSA

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“…To make the algorithm robust in nature and improve the efficiency, real time hardware implementation is a most acceptable solution. The hardware implementations of DE, RCM, histogram bin exchange, wavelet transform and channel coding algorithms have been observed [30]- [34]. The comparative results between these and proposed algorithm based on hardware resources utilization are presented.…”

Section: Introductionmentioning

confidence: 99%

Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking

et al. 2020

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This paper presents an improved reversible contrast mapping (RCM) algorithm for reversible invisible watermarking (RIW) in both software and hardware platforms. Based on well-known parameters for RIW like distortion, embedding bit rate, payload size and data hiding capacity, an efficient embedding bit rate control based contrast mapping (EBCRCM) algorithm is proposed. An adaptive linear contrast mapping on pixel intensity value is asserted with RCM that controls the embedding bit rate without changing the embedding capacity to maintain distortion. Xilinx system generator (XSG) and VIVADO tool construct the novel VLSI architecture that needs 173.362 ns latency for 100 MHz clock with throughput 46.146 Mbps and 5.8 ns critical path for single cycle of embedding process. The proposed algorithm is verified in MATLAB tool based software platform by taking different types of multimedia data like gray-scale images, color images and video signals. Implementation of low hardware resources based VLSI architecture through zed-board in real time field programmable gate array (FPGA) platform confirms the capability of high speed, low cost and real-time use. 100% agreement is observed from software simulations and hardware platforms.INDEX TERMS Reversible image watermarking, reversible contrast mapping, Xilinx system generator, FPGA.

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FPGA implementation of robust and low complexity template-based watermarking for digital images

Dzhanashia,

Evsutin

2023

Multimed Tools Appl

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Parallel hardware implementation of data hiding scheme for quality access control of grayscale image based on FPGA

Cited by 5 publications

References 28 publications

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking

FPGA implementation of robust and low complexity template-based watermarking for digital images

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