Parallel correlated double sampling technique for pipelined analogue-to-digital converters

Sadrafshari

Hadidi

et al. 2011

In this paper a new operational amplifier is presented based on the conventional folded cascode Op-Amp structure. A new method of positive feedback is used to increase DC-gain. Contrary to conventional designs this method does not decrease the speed of the folded cascode Op-Amp in the closed loop configuration. Simplicity is the other advantage of the proposed Op-Amp in comparison with the conventional structures. In this method, DC-gain improves by adding only two devices to the folded cascode structure. The additional devices neither decrease the bandwidth nor increase the power consumption, to a great extent. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.35 lm CMOS technology. HSPICE simulation confirms the theoretical estimated improvements.

Section: Introductionmentioning

confidence: 99%

Fast-settling CMOS Op-Amp with improved DC-gain

Sadrafshari

Hadidi

et al. 2011

“…But since the dominant pole does not occur in the output node, miller compensation capacitor is needed which reduces the bandwidth of the amplifier. Also, in Correlated Double Sampling (CDS) [3] and Correlated Level Shifting (CLS) [4] methods, two clock cycles are needed to amplify, so the speed may be reduced. Positive feedback can also be used to achieve higher dc-gain [5,6].…”

Section: Introductionmentioning

confidence: 99%

An enhanced folded cascode Op-Amp using positive feedback and bulk amplification in 0.35 μm CMOS process

Sadrafshari

Hadidi

et al. 2010

In this paper a new operational amplifier is presented which is based on the conventional folded cascode Op-Amp structure. A new method of positive feedback is used to increase dc-gain. This method does not limit the range of the output voltage swing. True performance of the Op-Amp in higher output voltage swings is another advantage of the proposed Op-Amp in comparison with the conventional structures. Bulk amplification and positive feedback are used to improve the Op-Amp specifications. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.35 lm CMOS technology. The HSPICE simulation confirms the theoretical estimated improvements.

“…Switch-capacitor techniques, such as correlated double-sampling (CDS) and correlated level shifting (CLS) are used to decrease errors from finite OTA gain [130][131][132]. As mentioned before, in the modern technologies with lower supply voltages, lower amplifier dc-gain and lower output swing range, are two limitations for the ULV analog circuits.…”

Section: High Dc-gain Amplifiers Usually Utilize Cascoding and Cascad...mentioning

confidence: 99%

Energy-efficient, fast-settling, modified nested-current-mirror, single-stage-amplifier for high-resolution LCDs in 90-nm CMOS

Berg

Mirmotahari

2018

In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.