Parallel Algorithms Development for Programmable Devices with Application from Cryptography

Abstract

Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), have been witnessing a considerable increase in density. State-of-the-art FPGAs are complex hybrid devices that contain up to several millions of gates. Recently, research effort has been going into higher-level parallelization and hardware synthesis methodologies that can exploit such a programmable technology. In this paper, we explore the effectiveness of one such formal methodology in the design of parallel versions of the Serpent cryptographic algorithm. The suggested methodology adopts a functional programming notation for specifying algorithms and for reasoning about them. The specifications are realized through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions. The refinements are inspired by the operators of Communicating Sequential Processes and map easily to programs in Handel-C (a hardware description language). In the presented research, we obtain several parallel Serpent implementations with different performance characteristics. The developed designs are tested under Celoxica's RC-1000 reconfigurable computer with its two million gates Virtex-E FPGA. Performance analysis and evaluation of these implementations are included.

HTCC: Haskell to Handel-C Hardware Compiler

“…Handel-C can target different FPGA types. Recent research effort has been on automating hardware generation to target Handel-C and hardware in general starting from functional specifications, such as, Haskell [6]- [9].…”

“…The adopted methodology refines functional specifications into parallel hardware implementations in Handel-C. Several case-studies for the methodology were carried out by Damaj et. al [9], [26]- [28], however the implementations did not include a compiler that automates the refinement procedure. Figure 1 depicts the step-wise refinement procedure, where functional specifications are refined to hardware.…”

“…The Stream is a purely sequential method of communicating a list of values. The Vector is a refinement of a simple list of items that communicates the entire structure in parallel [9].…”

“…The refinement of higher-order functions to processes could be done in stream or vector settings, or a combination of them. In Handel-C, datatypes are refined to structures (struct), while processes are refined to macro procedures [9]. Handel-C compiler generates the required hardware circuits that can be mapped onto FPGAs.…”

Synthesis of multi-level pipelines for programmable logic devices

“…al [2], [3], [4] that adopts the transformational programming approach for deriving parallel algorithms from functional specifications (See Figure 1). In this approach, the functional notation is used for specifying algorithms.…”