HTCC: Haskell to Handel-C Hardware Compiler

Abstract

Functional programming languages, such as Haskell, enable simple, concise, and correct-by-construction hardware development. HTCC compiles a subset of Haskell to Handel-C language with hardware output. Moreover, HTCC generates VHDL, Verilog, EDIF, and SystemC programs. The design of HTCC compiler includes lexical, syntax and semantic analyzers. HTCC automates a transformational derivation methodology to rapidly produce hardware that maps onto Field Programmable Gate Arrays (FPGAs) . HTCC is generated using ANTLR compiler-compiler tool and supports an effective integrated development environment. This paper presents the design rationale and the implementation of HTCC. Several sample generations of first-class and higher-order functions are presented. In-addition, a compilation case-study is presented for the XTEA cipher. The investigation comprises a thorough evaluation and performance analysis. The targeted FPGAs include Cyclone II, Stratix IV, and Virtex-6 from Altera and Xilinx.

Modelling and verification of parameterized architectures: A functional approach

“…Throughout this work, we will use plain Haskell (to deeply exploit its powerful features) instead of a functional HDL (Hardware Description Language). General Haskell could be subsequently translated into a restricted intermediate representation [29,30] before translating it to an imperative HDL like VHDL, or Verilog.…”