Parallel algorithm for computation of deadlocks and traps in Petri nets

Węgrzyn, Agnieszka

doi:10.1109/etfa.2005.1612513

Cited by 4 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed method of analyzing of Petri net checks liveness and looks for any possible defects [13]. When Petri net is correct the coloring is preformed.…”

Section: A Analysis Of Petri Net By Using Sequent Calculus Systemmentioning

confidence: 99%

UML Modelling in Rigorous Design Methodology for Discrete Controllers

Łabiak¹,

Adamski²,

Doligalski³

et al. 2012

International Journal of Electronics and Telecommunications

View full text Add to dashboard Cite

The paper presents an application of UML technology in a discrete system development process. In the process at the analysis stage UML diagrams are fundamental tool. The outcome of this stage is a basis for formal models exploited at the design stage, where the design is symbolically verified and treated as a rule-based system. Two formal models of good graphical appeal are proposed: Petri nets and state machine diagrams. Both are heavily using Boolean expressions what makes that design can easily be implemented in modern programmable structures.

show abstract

“…The proposed method of analyzing of Petri net checks liveness and looks for any possible defects [13]. When Petri net is correct the coloring is preformed.…”

Section: A Analysis Of Petri Net By Using Sequent Calculus Systemmentioning

confidence: 99%

UML Modelling in Rigorous Design Methodology for Discrete Controllers

Łabiak¹,

Adamski²,

Doligalski³

et al. 2012

International Journal of Electronics and Telecommunications

View full text Add to dashboard Cite

show abstract

“…In this case Petri nets (PNs) [8], [9] are one of the most adequate methods for formal design of ASLCs [10]. It gives easy way for representation of concurrent processes and additionally there could be applied mathematical algorithms for formal analysis and verification of the designed model [11]- [17]. There are also several algorithms of direct synthesis of Petri net model into FPGA devices [18]- [21].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA

Bukowiec¹,

Tkacz²,

Gratkowski³

et al. 2013

International Journal of Electronics and Telecommunications

View full text Add to dashboard Cite

Abstract-In the paper an implementation of algorithm of Petri net array-based synthesis is presented. The method is based on decomposition of colored interpreted macro Petri net into subnets. The structured encoding of places in subnets is done of using minimal numbers of bits. Microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a twolevel concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. This algorithm is implemented in C# and delivered as a stand alone library.

show abstract

“…In this case Petri nets (PNs) [6], [7] are one of the most adequate methods for formal design of application specific logic controllers [1]. It gives easy way for representation of concurrent processes and additionally there could be applied mathematical algorithms for formal analysis and verification of the designed model [8]- [11]. There are also several algorithms of direct synthesis of Petri net model into FPGA devices [12]- [15].…”

Section: Introductionmentioning

confidence: 99%

Synthesis of Macro Petri Nets into FPGA with Distributed Memories

Bukowiec¹,

Adamski²

2012

International Journal of Electronics and Telecommunications

View full text Add to dashboard Cite

Abstract-In this paper a new method of Petri net array-based synthesis is proposed. The method is based on decomposition of colored interpreted macro Petri net into state machine subnets. Each state machine subnet is determined by one color. During the decomposition process macroplaces are expanded or replaced by doublers of macroplace. Such decomposition leads to parallel implementation of a digital system. The structured encoding of places is done by using minimal numbers of bits. Colored microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.

show abstract

Parallel algorithm for computation of deadlocks and traps in Petri nets

Cited by 4 publications

References 4 publications

UML Modelling in Rigorous Design Methodology for Discrete Controllers

UML Modelling in Rigorous Design Methodology for Discrete Controllers

Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA

Synthesis of Macro Petri Nets into FPGA with Distributed Memories

Contact Info

Product

Resources

About