PARADISE: Design Environment for Para llel &amp; Dis tributed, E mbedded Real-Time Systems

Hardt, Wolf‐Dietrich; Altenbernd, P.; Böke, Carsten; Castillo, Giuseppe Del; Ditze, C.; Erpenbach, E.; Glässer, Uwe; Kleinjohann, Bernd; Lehrenfeld, G.; Rammig, Franz J.; Rust, Carsten; Stappert, Friedhelm; Stroop, Joachim; Tacken, Jürgen

doi:10.1007/978-0-387-35570-2_16

Cited by 3 publications

(3 citation statements)

References 4 publications

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“…In the case of distributed real-time software one compiles the corresponding PrlT-subnet using the ~-LAB Hard Real-Time System (CHaRy) (Altenbernd, 1997). These tools are both parts of the PARADISE Design Environment (Hardt, 1998).…”

Section: Synthesismentioning

confidence: 99%

Using Extended Predicate/Transition-Nets for the Specification, Analysis and Synthesis of Embedded Real-Time Systems

Tacken

1999

Distributed and Parallel Embedded Systems

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Section: Synthesismentioning

confidence: 99%

Using Extended Predicate/Transition-Nets for the Specification, Analysis and Synthesis of Embedded Real-Time Systems

Tacken

1999

Distributed and Parallel Embedded Systems

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“…Both, the template and the parameters can be changed easily for further design space exploration. Our approach has been implemented and was integrated into the PARADISE design environment [2]. This paper is structured as follows.…”

Section: Introductionmentioning

confidence: 99%

Architechture level optimization for asynchronous IPs

Hardt

Visarius²,

Kleinjohann³

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

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In this paper we present a customized approach to performance and area optimization of asynchronous functional blocks. First an abstract model of the block architectwe is introduced and an analytical method for throughput maximization is described. Secondly, area optimization can be performed with respect to data dependencies and merged data paths. These methods have been implemented and validated by several examples. A first chip implementing all relevant architecture blocks has been produced. The chip is named FLYSIG~ and operates completely delay-insensitive.

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“…The specific architecture characteristics are not reflected within a standard FPGA proto- 1 The authors would like to ackknowledge the support provided by Deutsche Forschungsgemeinschaft DFG, project SPP RP. 2 dataFLow oriented delaY-insensitive SIGnal processing typing architecture. Thus, functional validation requires complex multi FPGA prototyping environments and performance validation -which is highly important for embedded real-time systems -cannot be performed by standard prototyping approaches for specialized target architectures.…”

Section: Introductionmentioning

confidence: 99%

The FLYSIG prototyping approach

Hardt

Kleinjoahann²,

Rettbergr³

Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path From Specification to Protot

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In 1 this paper we presents a customized approach to rapid prototyping based on a new chip design. The chip is named FLYSIG 2 and adapts the prototyping architecture to the target architecture and the application domain in view. The chip architecture is scalable according to the requirements of arithmetic operators and interconnection flexibility. The prototyping chip is configurable in terms of operator functionality and operator interconnection. A FL-YSIG prototyping chip with 720 add / sub operators has been already been designed and a smaller version is just running through the fab. The design process of FLYSIG based rapid prototyping is supported by tools providing automated scheduling, performance analysis and code generation. The FLYSIG prototyping approach is illustrated by an example of reasonable complexity, i.e. a nested loop convolution algorithm which could be prototyped with the FLYSIG approach easily.

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PARADISE: Design Environment for Para llel & Dis tributed, E mbedded Real-Time Systems

Cited by 3 publications

References 4 publications

Using Extended Predicate/Transition-Nets for the Specification, Analysis and Synthesis of Embedded Real-Time Systems

Using Extended Predicate/Transition-Nets for the Specification, Analysis and Synthesis of Embedded Real-Time Systems

Architechture level optimization for asynchronous IPs

The FLYSIG prototyping approach

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