PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures

Cattaneo, Riccardo; Bellini, Riccardo; Durelli, Gianluca; Pilato, Christian; Santambrogio, Marco D.; Sciuto, D.

doi:10.1109/ipdpsw.2014.32

Cited by 13 publications

(20 citation statements)

References 13 publications

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“…In [12], the authors present the PaRA-Sched automated design methodology. This takes into account DPR in the scheduling infrastructure to improve overall performance by automatically masking reconfiguration time when possible.…”

Section: Related Workmentioning

confidence: 99%

Can real-time systems benefit from dynamic partial reconfiguration?

Pezzarossa

Kristensen

Schoeberl

et al. 2017

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Abstract-In real-time systems, a solution where hardware accelerators are used to implement computationally intensive tasks can be easier to analyze, in terms of worst-case execution time (WCET), than a pure software solution. However, when using FPGAs, the amount and the complexity of the hardware accelerators are limited by the resources available. Dynamic partial reconfiguration (DPR) of FPGAs can be used to overcome this limitation by replacing the accelerators that are only required for limited amounts of time with new ones. This paper investigates the potential benefits of using DPR to implement hardware accelerators in real-time systems and presents an experimental analysis of the trade-offs between hardware utilization and WCET increase due to the reconfiguration time overhead of DPR. We also investigate the trade-off between the use of multiple specialized accelerators combined with DPR instead of the use of a more general accelerator. The results show that, for computationally intensive tasks, the use of DPR can lead to a more efficient use of the FPGA, while maintaining comparable computational performance.

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Section: Related Workmentioning

confidence: 99%

Can real-time systems benefit from dynamic partial reconfiguration?

Pezzarossa

Kristensen

Schoeberl

et al. 2017

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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“…In literature there are many approaches addressing variants of the RCSP problem that rely on heuristic algorithms ( [2], [5]- [7], [10], [11]) and exact algorithms ( [2]- [4], [8], [12]). What follows is a description of these works in which we highlight their contributions and limitations.…”

Section: Related Workmentioning

confidence: 99%

“…Another approach is suggested in [2], where, by means of a reconfiguration-aware scheduler called Napoleon, it targets FPGA-based architectures with more than one 2D reconfigurator and takes into account both module reuse and reconfiguration prefetching, but it only optimizes the schedule duration. A last noteworthy heuristic is PaRA-Sched [10], a scheduler that takes advantage of Ant Colony Optimization (ACO). The algorithm considers all the previous cited features and techniques during the design space exploration.…”

Section: Related Workmentioning

confidence: 99%

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A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures

Deiana

Rabozzi

Cattaneo

et al. 2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Abstract-Designing applications for heterogeneous systems, like Multiprocessor System-on-Chips (MPSoCs) based on Field Programmable Gate Arrays (FPGAs) is a complex task. In order to exploit all the capabilities of these systems, such as Partial Dynamic Reconfiguration (PDR) and hardware acceleration, the designer still has to develop large parts of the system unassisted, establishing the design choices (i.e., whether to assign a task of the application on a hardware region of the FPGA or a general purpose processor of the SoC) mostly on his/her experience.In this paper we present a Mixed-Integer Linear Programming (MILP) formulation for mapping and scheduling of applications on heterogeneous and reconfigurable devices taking into account PDR, module reuse and configuration prefetching. Starting from a target architecture and a description of the application in terms of tasks and data dependencies, the proposed formulation allows the designer to optimize a linear combination of different metrics such as execution time, peak power and energy consumption.

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“…The exploration phase represented in Figure 1 starts from reading 4 input parameters from the XML files, which are the application task graph, the architecture description, the implementations associated with each task and the Design Space Exploration parameters to be used. After analyzing the input task graph, the toolchain assembles the information into an intermediate representation format that will be further manipulated by the mapper [9] and the scheduler [10]. After this initial step, the task graph is manipulated by the mapper, which will tightly interact with the scheduler to generate a mapping characterized by some performance metrics like execution time (an information computed by the scheduler) and the amount of utilized resources, which is computed from the board specifications and implementation details.…”

Section: Toolchain For Hw/sw Codesignmentioning

confidence: 99%

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board

Spada

Scolari

Durelli

et al. 2014

2014 IEEE International Symposium on Parallel and Distributed Processing With Applications

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Abstract-Even though FPGAs are becoming more and more popular as they are used in many different scenarios like communications and HPC, the steep learning curve needed to work with this technology is still the major limiting factor to their full success. Many works proposed to mitigate this problem by creating a companion of tools to support the designer during the development phase for this technology.The EU FASTER Project aims at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework relies in the fact that the partial dynamic reconfiguration, which FPGA devices can exploit, is seen as a first class citizen throughout the whole design flow. This work reports a case study in which the FASTER toolchain has been used to port a raytracer application onto the STM Spear prototyping embedded platform. The paper discusses the steps done for the realization of the prototype and the results obtained on the target device. It finally reports some improvements that can be exploited to improve the performance of the hardware implementation that has been realized.

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PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures

Cited by 13 publications

References 13 publications

Can real-time systems benefit from dynamic partial reconfiguration?

Can real-time systems benefit from dynamic partial reconfiguration?

A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board

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