[Paper] A 20Mfps Global Shutter CMOS Image Sensor with Improved Light Sensitivity and Power Consumption Performances

Abstract

the signal readout circuitry with decreased supply voltage of 3.3 V, the fill factor, the conversion gain and the readout gain were all improved from the previous chip and an eight times higher light sensitivity and a 50 % decrease of power consumption were achieved simultaneously. The impact of the performance improvements was confirmed to be significant based on the captured movie video of UHS phenomena.

Over 100 Million Frames per Second 368 Frames Global Shutter Burst CMOS Image Sensor with Pixel-wise Trench Capacitor Memory Array

“…On the other hand, the pixel and the memory array in this work are placed close and connected by about 200 µm relatively short output lines. Figure 15b shows the comparison of the current consumption per pixel during video capturing at the maximum frame rate between the previous work [8] and this work. All the current values were estimated by the circuit simulation.…”

“…Without a large cooling mechanism, the system can be miniaturized and lightened and can be easily used in various environments. Figure 15a shows the pixel arrangement of the previously developed burst CMOS image sensors [7,8] and the developed burst CMOS image sensor of this work. In previous works, the pixel and the memory array are separated in place and connected by about 8 mm long pixel output lines with the relay source follower buffer (Relay SF).…”

“…The burst complementary metal-oxide-semiconductor (CMOS) image sensor technology having multiple analog voltage domain memories connected to each pixel is another candidate to achieve such high frame rate with long record length and acceptable power consumption. Figure 1 shows structures of burst CMOS image sensors [6], where Figure 1a shows the previously developed chip with memory array placed on the periphery of pixel array achieved 20 Mfps with up to 256 record length [7,8], Figure 1b shows an improved structure of Figure 1a with increased number of pixels and record length by high density memory array [9,10], and Figure 1c shows a planar structure with pixel-wise high density memory array [11][12][13]. Recently, we have developed a prototype CMOS image sensor of Figure 1c with conventional planar MOS capacitor memory array [12,13].…”

“…The size of one transistor and one trench capacitor memory cell is 1.4 H µm × 2.0 V µm. It achieves about four times higher memory cell density than conventional planar MOS capacitor cell both using 0.18 µm CMOS technology [7,8]. Figures 6 and 7 show the timing diagram of the memory selection pulses and the pixel driving pulses at burst video capturing with in-pixel and off-pixel CDS operation, respectively.…”

High-Speed <italic>In Situ</italic> Observation System for Sonoporation of Cells With Size- and Position-Controlled Microbubbles

“…High-contrast observation of a biological cell is also important for high-speed studies on bubble-cell interaction. High-image quality is one of the advantages of a high-speed camera that uses a sensitive CMOS image sensor with 128 on-chip memories [34].…”