PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer

Tang, Liangxiao; Gai, Weixin; Shi, Linqi

doi:10.1109/iscas.2016.7539030

Cited by 8 publications

(2 citation statements)

References 6 publications

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“…However, the design process limits the speed of receivers. In conventional analog design, three comparators can be used to decode a PAM4 signal [13,14,15,16,17,18,19,20,21,22,23,24] by transforming it via three threshold voltages into a 3-digit thermometer code. These receivers are almost realized by analog circuit, excluding the threshold and DFE adaptation logics, and can reach very high speed.…”

Section: Introductionmentioning

confidence: 99%

“…Although this receiver does use relatively few comparators, changes in common-mode voltage may affect the accuracy of amplitude rectification. To determine the threshold voltage, the conventional PAM4 receiver first detects 4 levels [21,23,24] and then determines the threshold voltage (the middle of the eye). Compared with the conventional receiver, a receiver based on amplitude-rectification should only distinguish 2 levels of the rectifier output; this greatly simplifies the threshold voltage adaptation process.…”

Section: Introductionmentioning

confidence: 99%

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A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

Han

Wang

2021

IEICE Electron. Express

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This paper presents a 56-Gbps four-level pulse amplitude modulation (PAM4) quarter-rate receiver based on amplitude rectification. Compared with the conventional three-comparator structure, the PAM4 signal is converted into a 2-digit gray-code rather than a 3-digit thermometer-code. The amplitude is detected to decode the least significant bit (LSB), which allows the proposed receiver to use significantly less power by reducing the number of comparators. An inverter-based common-mode voltage stabilization circuit (CVSC) is proposed to reduce the effect of common-mode level changes as the amplitude is determined. To minimize the feedback delay, the 2-digit gray-code is fed back to DFE's summer directly. By reducing the digit of the feedback signal, the power will be further reduced as the DFE tap increases. The device consumes 83.5 mW over a 55-nm process.

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