PAM-Blox: high performance FPGA design for adaptive computing

Abstract

PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High-performance FPGA design for adaptive computing is simplified by using a hierarchy of optimized hardware objects described in C++.PAM-Blox consist of two major layers of abstraction. First, PamBlox are parameterizable simple elements such as counters and adders. Automatic placement of carry chains and flexible shapes are supported. PaModules are more complex elements possibly instantiating PamBlox. PaModules have fixed shapes and are usually optimized for a specific data-width. Examples for PaModules are multipliers, Coordinate Rotations (CORDICs), and special arithmetic units for encryption.The key difference of our approach to most other design tools for FPGAs is that the designer has total control over placement at each level of the design hierarchy, which is the key to high-performance FPGA design. Second, the object interface was chosen carefully to encourage code-reuse and simplify code-sharing between designers.PAM-Blox are intended to be part of an open library that allows design sharing between members of the adaptive computing community.

Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs

“…Our approach differs from other efforts to develop high-level programming languages for reconfigurable computing, which commonly augment sequential languages such as C, C++, and Java with support for data-parallel operations and hardware layouts [1,6,2,9]. While such languages have been sucessfully used to design efficient applications, they emphasize a signal-oriented view of computation, do not allow concurrency to be expressed naturally, and they do not attempt to target the run-time reconfigurable capabilities of the hardware.…”

Power and energy efficiency evaluation for HW and SW implementation of nxn matrix multiplication on Altera FPGAs

“…To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Other related work is done by Oskar Mencer, Martin Morf and Michael J. Flynn in [5], within Xlinx platform where they compared the throughput of 4x4 matrix multiplier in three different designs. The first design which suffices with the Synopsys FPGA Express II complier and multiple bit-serial multipliers using booth encoding performs the matrix multiplication in 39 clock ticks and allow 15 MHz as the maximum operating frequency, while the other last two designs which employ the parameterized circuit generators with different multiplication algorithm reduce the latency by 31% and 51% of the first design and permit 33 MHz as the maximum operating frequency.…”

Object-oriented domain specific compilers for programming FPGAs

“…1. The infrastructure consists of PAM-Blox [7], an object-oriented module-generation environment. On top of PAM-Blox, we build domain specific compilers.…”