Packet Reordering in Network Processors

Govind, Shamitha; Govindarajan, Raghav; Kuri, Joy

doi:10.1109/ipdps.2007.370287

Cited by 23 publications

(10 citation statements)

References 10 publications

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“…First, the NP can allocate a global sequence number to every arriving packet [20], [21]. However, this solution also incurs a high reordering delay, because all packets are treated as a single flow, the order of which has to be preserved.…”

Section: B Related Workmentioning

confidence: 99%

“…However, as explained in [16], it is not scalable to a large number of network flows because of the large number of needed counters. A third method to avoid packet reordering is to keep an inter-thread signaling system between the cores [20]. However, in NPs with a high degree of parallelism and a high clock frequency, this method can be complex to implement.…”

Section: B Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Scaling multi-core network processors without the reordering bottleneck

Shpiner

Keslassy

Cohen³

2014

2014 IEEE 15th International Conference on High Performance Switching and Routing (HPSR)

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Today, designers of network processors strive to keep the packet reception and transmission orders identical, and therefore avoid any possible out-of-order transmission. However, the development of new features in advanced network processors has resulted in increasingly parallel architectures and increasingly heterogeneous packet processing times, leading to large reordering delays. In this paper, we introduce novel scalable scheduling algorithms for preserving flow order in parallel multi-core network processors. We show how these algorithms can reduce reordering delay while adapting to any load-balancing algorithm and keeping a low implementation complexity overhead. To do so, we use the observation that all packets in a given flow have similar processing requirements and can be described with a constant number of logical processing phases. We further define three possible knowledge frameworks of the time when a network processor learns about these logical phases, and deduce appropriate algorithms for each of these frameworks.

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Section: B Related Workmentioning

confidence: 99%

Section: B Related Workmentioning

confidence: 99%

Scaling multi-core network processors without the reordering bottleneck

Shpiner

Keslassy

Cohen³

2014

2014 IEEE 15th International Conference on High Performance Switching and Routing (HPSR)

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“…This adversely affects some network applications [8,27]. Thus reorder buffers and logic are usually needed, which are expensive and complicated.…”

Section: Partitioning-based Parallel Ip Lookup Enginesmentioning

confidence: 99%

Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines

Jiang¹,

Prasanna²

2009

Journal of Parallel and Distributed Computing

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“…It affects adversely some network applications [8,23]. Thus reorder buffers and logic are usually needed, which are expensive and complicated.…”

Section: Partition-based Parallel Ip Lookup Enginesmentioning

confidence: 99%

Parallel IP lookup using multiple SRAM-based pipelines

Jiang

Prasanna

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high throughput IP lookup. Multiple pipelines can be utilized in parallel to improve the throughput further. However, several challenges must be addressed to make such solutions feasible. First, the memory distribution over different pipelines as well as across different stages of each pipeline must be balanced. Second, the traffic among these pipelines should be balanced. Third, the intra-flow packet order should be preserved. In this paper, we propose a parallel SRAM-based multi-pipeline architecture for IP lookup. A two-level mapping scheme is developed to balance the memory requirement among the pipelines as well as across the stages in a pipeline. To balance the traffic, we propose a flow pre-caching scheme to exploit the inherent caching in the architecture. Our technique uses neither a large reorder buffer nor complex reorder logic. Instead, a payload exchange scheme exploiting the pipeline delay is used to maintain the intra-flow packet order. Extensive simulation using real-life traffic traces shows that the proposed architecture with 8 pipelines can achieve a throughput of up to 10 billion packets per second (GPPS) while preserving intra-flow packet order.

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Packet Reordering in Network Processors

Abstract: Network processors today consists of multiple parallel processors (microengines)

Cited by 23 publications

References 10 publications

Scaling multi-core network processors without the reordering bottleneck

Scaling multi-core network processors without the reordering bottleneck

Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines

Parallel IP lookup using multiple SRAM-based pipelines

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