Parallel IP lookup using multiple SRAM-based pipelines

Abstract

Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high throughput IP lookup. Multiple pipelines can be utilized in parallel to improve the throughput further. However, several challenges must be addressed to make such solutions feasible. First, the memory distribution over different pipelines as well as across different stages of each pipeline must be balanced. Second, the traffic among these pipelines should be balanced. Third, the intra-flow packet order should be preserved. In this paper, we propose a parallel SRAM-based multi-pipeline architecture for IP lookup. A two-level mapping scheme is developed to balance the memory requirement among the pipelines as well as across the stages in a pipeline. To balance the traffic, we propose a flow pre-caching scheme to exploit the inherent caching in the architecture. Our technique uses neither a large reorder buffer nor complex reorder logic. Instead, a payload exchange scheme exploiting the pipeline delay is used to maintain the intra-flow packet order. Extensive simulation using real-life traffic traces shows that the proposed architecture with 8 pipelines can achieve a throughput of up to 10 billion packets per second (GPPS) while preserving intra-flow packet order.

Large-scale wire-speed packet classification on FPGAs

“…We use a heuristic similar to our previous study of trie-based IP lookup [8], which allows the nodes on the same level of the tree to be mapped onto different stages. This provides more flexibility to map the tree nodes, and helps achieve a balanced memory and node distribution across the stages in a pipeline, as shown in Figure 5.…”

Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines

“…This paper aims to eliminate them, by exploiting the processing delay in the pipelines. The initial version of the paper [11] proposes a payload exchange scheme, which however can only reorder the last two packets of a flow. The payload exchange scheme cannot prevent the new packet going out of order with some other preceding packets of the flow.…”

Reducing dynamic power dissipation in pipelined forwarding engines

“…As the network traffic grows rapidly, IP forwarding becomes a major performance bottleneck for network routers [1], [2]. For example, current backbone link rates have been pushed beyond OC-768 (40 Gbps) rate, which requires a throughput of 125 million packets per second (MPPS) for minimum size (40 bytes) packets.…”

“…dominate today's high-end routers. However, as a result of the massive parallelism inherent in their architecture, TCAMs do not scale well in terms of clock rate, power consumption, or chip density [2]. It is estimated that the power consumption per bit of TCAMs is on the order of 3 micro-Watts, which is 150 times that of Static Random Access Memories (SRAMs) [3].…”

“…It is estimated that the power consumption per bit of TCAMs is on the order of 3 micro-Watts, which is 150 times that of Static Random Access Memories (SRAMs) [3]. On the other hand, most SRAM-based algorithms can be implemented as some form of tree traversal, such as trie-based algorithms [7], which can be pipelined to achieve a high throughput of one packet per clock cycle [2]. Though SRAM-based pipeline solutions are being considered as attractive alternatives to TCAMs [2], they still suffer from high power consumption [8], due to the large number of memory accesses.…”