Packet header analysis and field extraction for multigigabit networks

Kobiersky, P.; Kořenek, Jan; Polčák, Libor

doi:10.1109/ddecs.2009.5012106

Cited by 16 publications

(3 citation statements)

References 7 publications

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“…By limiting the unit and range of selection fields, resource consumption can be effectively reduced while ensuring rationality [22]. In the work of [23], an efficient header analysis and field extraction architecture is proposed for FPGA-based network applications. In the design of dRMT [24], to reduce the overhead of the input crossbar in the action engine, only 32 ALU parallel operations are present in each pipeline stage, and the corresponding fields are written back to the PHV through the output crossbar.…”

Section: Related Workmentioning

confidence: 99%

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

Song,

Lu,

Guo

2024

Micromachines

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As the key module of programmable switches or the SmartNIC card, the packet processing pipeline undertakes the task of packet forwarding and processing. However, the current pipeline for the FPGA-based SmartNIC is inflexible, and the related reconfigurable commercial device designs are closed-source. To solve this problem, this paper proposes a high-performance reconfigurable pipeline design, which has fully reconfigurable match-action units, supporting various network functions by its flexible reconfiguration. The fields of the match key and the size of the match table can be reconfigured without recompiling the HDL code or modifying the hardware. The processing rules and action instructions for the pipeline can be dynamically installed by the configuration module at runtime. We implement our design on the Xilinx Alveo U200 board with a Virtex UltraScale+ XCU200-2FSGD2104E FPGA and show that the designed pipeline supports fast reconfiguration to implement new network functions and that the throughput of the designed pipeline reaches 100 Gbps with low latency.

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Section: Related Workmentioning

confidence: 99%

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

Song,

Lu,

Guo

2024

Micromachines

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“…Petr Kobiersky et al proposed a packet header analysis architecture based on a Virtex-5 FPGA device [3]. The implemented modules are able to operate on 20 Gbps network links, where the parser module is generated from XML protocol scheme.…”

Section: Related Workmentioning

confidence: 99%

Line-rate packet processing in hardware: the evolution towards 400 Gbit/s

Tóthfalusi¹,

Orosz

2015

Proceedings of the 9th International Conference on Applied Informatics, Volume 1

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Network packet parsing and packet forwarding are general tasks for all routing devices. However, the requirement for line-rate packet processing, independently from the transmission technology, is a common demand against core network equipments. In this paper, we investigate programmable hardware architectures (i.e., Field Programmable Gate Array -FPGA) as central building blocks of the data plane for state-of-the-art 100 Gbit/s network devices. We reveal the benefits and drawbacks of the available hardware architectures (such as Network Processors, Application-Specific Integrated Circuits (ASIC) and FPGAs, respectively). After showing the general packet processing steps on programmable hardware, we describe the problem space of line-rate packet processing in relation to the evolution of transmission technologies, i.e., 1, 10, 100 Gbit/s Ethernet and beyond. Moreover, we present design trade-offs, such as operational frequency, data path width and resource requirement, covering the 1 to 400 Gbit/s throughput range and we propose best practices for their hardware designs.

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“…Kobierský et al [3] describe the packet headers in XML and generate finite state machines, which parse the described protocol stack. However, the number of states in FSMs rises rapidly with the width of the data bus.…”

Section: Related Workmentioning

confidence: 99%

Design methodology of configurable high performance packet parser for FPGA

Pus

Kekely

Kořenek

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.

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Packet header analysis and field extraction for multigigabit networks

Cited by 16 publications

References 7 publications

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

Line-rate packet processing in hardware: the evolution towards 400 Gbit/s

Design methodology of configurable high performance packet parser for FPGA

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