Design methodology of configurable high performance packet parser for FPGA

Pus, Viktor; Kekely, Lukáš; Kořenek, Jan

doi:10.1109/ddecs.2014.6868788

Cited by 9 publications

(7 citation statements)

References 5 publications

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“…Table I shows the comparison between the proposed solution with a 512-bit wide datapath and other packet parser designs on Virtex 7 XC7VXH870T. Results are given for a TCPandIP4andIP6 specialized parser after synthesis for the proposed design and [17], and after implementation for [20]. In order to provide a fair comparison between the related works and the proposed architecture, the parser was configured with 3 header parsers, 3 feature analyzers and 64-bit feature width.…”

Section: Test Results and Resource Usagementioning

confidence: 99%

“…Despite its high flexibility, the proposed approach has a comparable resource usage with [20], but greatly improves the latency and the flexibility. Comparison with [17] is difficult on a fair basis, since this solution is very dedicated, with almost no flexibility. Resource usage is 2.5 times as large for the proposed solution, but it stays acceptable.…”

Section: Test Results and Resource Usagementioning

confidence: 99%

“…Pus et al [17] presented a pipelined design of packet header parsers reaching data rates of 100 Gb/s. This parser architecture supports an automatic high level parser generation tool [18].…”

Section: Configurable Solutionsmentioning

confidence: 99%

See 2 more Smart Citations

Open-source flexible packet parser for high data rate agile network probe

Cornevaux-Juignet

Arzel

Horrein

et al. 2017

2017 IEEE Conference on Communications and Network Security (CNS)

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The development of a network centered life has increased overall data rates in core networks. Thus, data centers face the challenge to provide always more services at higher data rates while reacting quickly to complex failures and more powerful attacks thanks to efficient network forensics. Moreover, Software-Defined Networking (SDN) becomes a standard which offers agility but also requires forensic devices able to handle multiple configurations. Although conventional software probes are programmable and thus agile, they cannot support high data rate packet processing any more. Probes could benefit from Application Specific Integrated Circuits (ASIC) to cope with high data rates, but ASICs development time of many months makes them unable to satisfy agility requirements. With reconfiguration ability and high throughput processing without packet loss, Field Programmable Gate Arrays (FPGA) are the key technology chosen by some companies, such as Microsoft, Amazon and OVH, to be integrated into smart Network Interface Cards (NIC). Nevertheless, while high performance criteria is fulfilled, current FPGA probes benefit from an agility still limited to their conventional firmware upgrades which require proprietary tools and hardware-design time and knowledge. This paper proposes the first solution to offer FPGA probes with runtime agility thanks to a flexible packet parser which can be parameterized continuously by a software, endorsing complex tasks and SDN control. This allows a live adaptation of protocol processings from computer host alongside handling packets at line rate without data loss. The proposed parser is opensource and easily usable by network engineers through a Python software API. Benchmark results illustrate the performance of the agile high-level probe implemented on a NetFPGA SUME board, with XC7VX690T FPGA. 60 millions of 64-byte packets are counted based on features provided at runtime. These are selected by the software part, allowing the detection of different volumetric attacks within a few tens of microseconds. This represents a 40 Gb/s traffic of smallest Ethernet packets with no packet loss. With adequate boards, the generic design of the probe offers 160 Gb/s data rates and beyond on modern hardware, assuring probe scalability.

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Section: Test Results and Resource Usagementioning

confidence: 99%

Section: Test Results and Resource Usagementioning

confidence: 99%

See 1 more Smart Citation

Open-source flexible packet parser for high data rate agile network probe

Cornevaux-Juignet

Arzel

Horrein

et al. 2017

2017 IEEE Conference on Communications and Network Security (CNS)

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show abstract

“…There are many approaches to FPGA packet parser published with many advantages and disadvantages [9]. Puš et al [2] proposed a hand-optimized pipelined packet parser. It used only 1.19% of the Virtex-7 870HT FPGA to achieve throughput over 100 Gb/s and 4.88% for throughput over 400 Gb/s with reasonable latency.…”

Section: Related Workmentioning

confidence: 99%

“…However, many problems are facing the design and the implementation of the parser such as (1) processing at a line rate in the high-speed network (parsing millions of packets per second), (2) adaptation to new protocols; the number and types of protocol types are varied (adding a new protocol needs an experienced designer acclimated to the HDL language or parser architecture), (3) incomplete information (some protocols have more one format: standard and customized), (4) the header fields attributes (number, size, and location) varied with the protocol type, (5) the parser must have a small size because of the restriction of the programmable device's size, and (6) the enormous hole between the product description and the hardware implementation in the device of new types protocol. These problems demand a programmable hardware packet parsing [2], [3]. Programmable packet parser relies on three steps: (1) highlevel protocol description, (2) automatic code generation, (3) dynamic reconfigurations.…”

Section: Introductionmentioning

confidence: 99%

HP4 High-Performance Programmable Packet Parser

Ibrahim¹

2022

Int. j. commun. netw. inf. secur.

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Now, header parsing is the main topic in the modern network systems to support many operations such as packet processing and security functions. The header parser design has a significant effect on the network devices' performances (latency, throughput, and resource utilization). However, the header parser design suffers from a lot number of difficulties, such as the incrementing in network throughput and a variety of protocols. Therefore, the programmable hardware packet parsing is the best solution to meet the dynamic reconfiguration and speed needs. Field Programmable Gate Array (FPGA) is an appropriate device for programmable high-speed packet implementation. This paper introduces a novel FPGA High-Performance Programmable Packet Parser architecture (HP4). HP4 automatically generated by the P4 (Programming protocol-independent Packet Processors) to optimize the speed, dynamic reconfiguration, and resource consumption. The HP4 shows a pipelined packet parser dynamic reconfiguration and low latency. In addition to high throughput (over 600 Gb/s), HP4 resource utilization is less than 7.5 percent of Virtex-7 870HT, and latency is about 88 ns. HP4 can use in a high-speed dynamic packet switch and network security.

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Performance Evaluation of Hardware Unit for Fast IP Packet Header Parsing

Efnusheva¹

2019

Intelligent Systems Applications in Software Engineering

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Design methodology of configurable high performance packet parser for FPGA

Cited by 9 publications

References 5 publications

Open-source flexible packet parser for high data rate agile network probe

Open-source flexible packet parser for high data rate agile network probe

HP4 High-Performance Programmable Packet Parser

Performance Evaluation of Hardware Unit for Fast IP Packet Header Parsing

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