Oxygen Plasma Damage in Boron‐Diffused Silicon

Abstract

CHLORINE LEVELS IN SiO2 419merits, the initial concentration near the silicon interface is too low (< 1El8 atom/cm~). High temperature annealing (1000~ is then needed to form a C1 peak at the interface, but in the process C1 evaporates up to 98% of the original content, losing the advantage of high C1 doping. This anneal and the high temperature cycle of LPCVD deposition are in conflict with current trends in very large scale integration to reduce the thermal budget. Since LPCVD oxide is used for interlevel dielectric after MOS source/drain formation, an extended thermal budget would increase the lateral diffusion of these regions and contribute to their encroachment below the channel. This severely limits MOS device scaling.For all these reasons, TCA oxidation appears superior, particularly since it has been proven effective at reduced temperature (900~ with the customary TCA content of 2.5 equiv, percent HC1. ABSTRACTTransistor p-n junctions are observed to have leaky electrical characteristics and increased resistivity after exposure to oxygen plasma. Heating the devices above 180~ for at least 10 min in vacuum, nitrogen, forming gas, or air eliminates the problem and returns the desired electrical characteristics. Experiments indicate that the increase in resistivity is associated with a boron displacement from silicon lattice sites. Additional experiments indicate that this phenomenon can be caused by reactively ion etching or plasma ashing a bare silicon surface which is doped with boron.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 155.69.4.4 Downloaded on 2015-06-04 to IP

Plasma Damage Induced on Silicon Surface in a Barrel Asher

“…The gallium-and aluminum-implanted wafers were placed near the front and rear ends of the holder, respectively. In the boron-implanted surface, we also see an increase in sheet resistance, which qualitatively agrees with the results by Frieser et al (11). A difference caused by different wafer positions in the reactor was also seen for boron-implanted wafers.…”

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