Overview of bus-based system-on-chip interconnections

In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. This has a huge impact on worst-case execution time (WCET) analysis and, in general, on the predictability of real-time applications implemented on such systems. As opposed to the WCET analysis performed for a single processor system, where the cache miss penalty is considered constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks' WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this paper we present an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures. The emphasis of this paper is on the bus scheduling policy and its optimization, which is of huge importance for the performance of such a predictable multiprocessor application.

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“…Such a policy can be used efficiently with the contemporary SoC buses, especially if QoS guarantees are required, [14,10,4].…”

Section: Bus Access Policymentioning

confidence: 99%

Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip

Rowe

Goel

Rajkumar

2007

28th IEEE International Real-Time Systems Symposium (RTSS 2007)

144

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“…Therefore, we are using a TDMA-based bus arbitration policy, which is suitable for modern system-on-chip designs with QoS constraints [11], [12], [1].…”

Section: B Bus Modelmentioning

confidence: 99%

Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip

Rosén

Eles

Peng

et al. 2011

2011 Sixth IEEE International Symposium on Electronic Design, Test and Application

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Abstract-Worst-case execution time analysis is the fundament of real-time system design, and is therefore an area which has been subject to great scientific interest for a long time. However, traditional worst-case execution time analysis techniques assume that the underlying hardware is a monoprocessor system, and this class of hardware platforms is getting less suitable for modern embedded applications, which demand more and more in terms of computational power. For multiprocessor systems, traditional worst-case analysis tools do not produce correct results and can consequently not be used. To solve this problem, we have previously proposed a technique for achieving predictability on multiprocessor systems-on-chip using a shared TDMA bus. One of the main benefits with our approach is that existing, traditional worstcase execution time analysis techniques can, after some small modifications, be applied. In this paper, we describe the nature of these modifications and how to handle different types of multiprocessor architectures.

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“…Therefore, we are using a TDMA-based bus arbitration policy, suitable for modern system-on-chip designs with QoS constraints [11], [12], [1], [13].…”

Section: Bus Modelmentioning

confidence: 99%

Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip

Rosén

Neikter

Eles

et al. 2011

2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium

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Abstract-Optimization techniques for improving the average-case execution time of an application, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this paper, we show that having a good average-case delay can be important also for real-time applications for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing the average case and the worst case simultaneously, allowing for a good average-case execution time while still keeping the worst case as small as possible.

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Overview of bus-based system-on-chip interconnections

Cited by 39 publications

References 8 publications

Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip

Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip

Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip

Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip

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