Overview of anneal technology for advanced logic CMOS

Abstract

This paper presents an overview of the anneal technology for advanced Logic CMOS technology nodes including Hk/MG stack. Junction engineering by ms-anneal has been studied, showing significant benefit in device scaling and fulfilling the stringent junction leakage requirement for low power applications. In addition, we highlight the implication of the metal gate integration flow ("Gate-First" / "Gate-Last") on junction design and also on eWF where we have proved that Vth is easily achievable with anneal sequence optimization. Finally we have reviewed the new applications of ms-anneal in logic CMOS process flow

Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

“…For further device scaling ( Fig. 2 & 3), aggressive Source and Drain implantation and junction anneal techniques are needed [4]. However, short channel control through aggressive Ultra Shallow Junction (USJ) scaling can often lead to a junction leakage increase, which represents a major challenge for LOP and LSTP technologies.…”