Overlay techniques for scratchpad memories in low power embedded processors

Verma, Manish; Marwedel, Peter

doi:10.1109/tvlsi.2006.878469

Cited by 59 publications

(62 citation statements)

References 32 publications

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“…This program managed memory implies a more complicated programming model. However, scratchpad memory can be automatically partitioned [3,1,49]. A similar approach for time-predictable caching is to lock cache blocks.…”

Section: Related Workmentioning

confidence: 99%

Data cache organization for accurate timing analysis

2012

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Caches are essential to bridge the gap between the high latency main memory and the fast processor pipeline. Standard processor architectures implement two first-level caches to avoid a structural hazard in the pipeline: an instruction cache and a data cache. For tight worst-case execution times it is important to classify memory accesses as either cache hit or cache miss. The addresses of instruction fetches are known statically and static cache hit/miss classification is possible for the instruction cache. The access to data that is cached in the data cache is harder to predict statically. Several different data areas, such as stack, global data, and heap allocated data, share the same cache. Some addresses are known statically, other addresses are only known at runtime. With a standard cache organization all those different data areas must be considered by worst-case execution time analysis. In this paper we propose to split the data cache for the different data areas. Data cache analysis can be performed individually for the different areas. Access to an unknown address in the heap does not destroy the abstract cache state for other data areas. Furthermore, we propose to use a small, highly associative cache for the heap area. We designed and implemented a static analysis for this cache, and integrated it into a worst-case execution time analysis tool.

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Section: Related Workmentioning

confidence: 99%

Data cache organization for accurate timing analysis

2012

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“…This program managed memory entails a more complicated programming model, although it can be automatically partitioned [1], [26]. Exposing the scratchpad memory at the language level can further help to optimize the time-critical path of the application.…”

Section: Cachingmentioning

confidence: 99%

Time-predictable chip-multiprocessor design

Schoeberl

2010

2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers

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Abstract-Real-time systems need time-predictable platforms to enable static worst-case execution time (WCET) analysis. Improving the processor performance with superscalar techniques makes static WCET analysis practically impossible. However, most real-time systems are multi-threaded applications and performance can be improved by using several processor cores on a single chip. In this paper we present a time-predictable chipmultiprocessor system that aims to improve system performance while still enabling WCET analysis.The proposed chip-multiprocessor (CMP) uses a shared memory with a time-division multiple access (TDMA) based memory access scheduling. The static TDMA schedule can be integrated into the WCET analysis. Experiments with a JOP based CMP showed that the memory access starts to dominate the execution time when using more than 4 processor cores. To provide a better scalability, more local memories have to be used. We add a processor local scratchpad memory and split data caches, which are still time-predictable, to the processor cores.

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“…Previous approaches for dynamic scratchpad allocation [15,26,27] have focused on the optimization of the average case. Data accesses statistics are typically computed from the execution profiling with a train input.…”

Section: Flowgraphs and Computation Of Worst-case Execution Path Infomentioning

confidence: 99%

“…An address assignment algorithm has been proposed in [27] to place data on scratchpad memory at compile-time.…”

Section: Memory Data Address Assignmentmentioning

confidence: 99%

“…Approaches for static [2] and dynamic [15,26,27] allocations have been designed to automatically place code and data on scratchpad memories. So far, many studies have been led on allocation of code and data on scratchpad memory for average execution time [2] or energy reduction [27]. A study [28] has demonstrated the superiority of scratchpad memory placement on some cache modeling techniques for execution time predictability of hard real-time systems.…”

Section: Introductionmentioning

confidence: 99%

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WCET-Directed Dynamic Scratchpad Memory Allocation of Data

Deverge

Puaut

2007

19th Euromicro Conference on Real-Time Systems (ECRTS'07)

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Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by software. The major gain is to enhance the predictability of memory accesses latencies. A compile-time dynamic allocation approach enables eviction and placement of data to the scratchpad memory at runtime.Previous dynamic scratchpad memory allocation approaches aimed to reduce average-case program execution time or the energy consumption due to memory accesses. For real-time systems, worst-case execution time is the main metric to optimize.In this paper, we propose a WCET-directed algorithm to dynamically allocate static data and stack data of a program to scratchpad memory. The granularity of placement of memory transfers (e.g. on function, basic block boundaries) is discussed from the perspective of its computation complexity and the quality of allocation.

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Overlay techniques for scratchpad memories in low power embedded processors

Cited by 59 publications

References 32 publications

Data cache organization for accurate timing analysis

Data cache organization for accurate timing analysis

Time-predictable chip-multiprocessor design

WCET-Directed Dynamic Scratchpad Memory Allocation of Data

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