WCET-Directed Dynamic Scratchpad Memory Allocation of Data

Deverge, Jean-François; Puaut, Isabelle

doi:10.1109/ecrts.2007.37

Cited by 77 publications

(79 citation statements)

References 22 publications

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“…Consequently, there are works that automatically allocate instructions and/or data onto the SPM [7,23]. SPM allocation techniques that are WCET-centric such as that proposed by Deverge and Puaut [7] and Suhendra et al [23] perform automatic allocation with the objective of reducing the worst-case execution path of the program. These works present innovative allocation techniques, but mainly for reducing the WCET of a single task.…”

Section: Motivationmentioning

confidence: 99%

“…There are two broad areas of research in SPM allocation: reduction of average-case execution time (ACET) [3,27], and reduction of worst-case execution time (WCET) [7,23]. General purpose systems use ACET methods, and hard real-time systems typically use WCET methods.…”

Section: Related Workmentioning

confidence: 99%

“…The authors in [7,23] propose data allocation schemes that focus on reducing the WCET of the program They identify a unique problem that is the WCET path may change with a single allocation of data. They first formulate the problem of static allocation of data to SPM as 0-1 ILP problem.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

An instruction scratchpad memory allocation for the precision timed architecture

Prakash¹,

Patel²

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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This work presents a static instruction allocation scheme for the precision timed architectures (PRET) scratchpad memory. Since PRET provides timing instructions to control the temporal execution of programs, the objective of the allocation scheme is to ensure that the explicitly specified temporal requirements are met. Furthermore, this allocation incorporates instructions from multiple hardware threads of the PRET architecture. We formulate the allocation as an integerlinear programming problem, and we implement a tool that takes binaries, constructs a controlflow graph, performs the allocation, rewrites the binary with the new allocation, and generates an output binary for the PRET architecture. We carry out experiments on a modified version of the Malardalen benchmarks to illustrate that commonly known ACET and WCET based approaches cannot be directly applied to meet explicit timing requirements. We also show the advantage of performing the allocation across multiple threads. We present a real time benchmark controlling an Unmanned Air Vehicle as the case study.iii

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Section: Motivationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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An instruction scratchpad memory allocation for the precision timed architecture

Prakash¹,

Patel²

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…A similar approach for time-predictable caching is to lock cache blocks. The control of the cache locking [30] and the allocation of data in the scratchpad memory [50,45,6] can be optimized for the WCET. A comparison between locked cache blocks and a scratchpad memory with respect to the WCET can be found in [31].…”

Section: Related Workmentioning

confidence: 99%

Data cache organization for accurate timing analysis

2012

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Caches are essential to bridge the gap between the high latency main memory and the fast processor pipeline. Standard processor architectures implement two first-level caches to avoid a structural hazard in the pipeline: an instruction cache and a data cache. For tight worst-case execution times it is important to classify memory accesses as either cache hit or cache miss. The addresses of instruction fetches are known statically and static cache hit/miss classification is possible for the instruction cache. The access to data that is cached in the data cache is harder to predict statically. Several different data areas, such as stack, global data, and heap allocated data, share the same cache. Some addresses are known statically, other addresses are only known at runtime. With a standard cache organization all those different data areas must be considered by worst-case execution time analysis. In this paper we propose to split the data cache for the different data areas. Data cache analysis can be performed individually for the different areas. Access to an unknown address in the heap does not destroy the abstract cache state for other data areas. Furthermore, we propose to use a small, highly associative cache for the heap area. We designed and implemented a static analysis for this cache, and integrated it into a worst-case execution time analysis tool.

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“…We have evaluated our approach by comparing with an ILPbased approach [2] and a longest-path-based greedy approach [22]. For the eight benchmarks selected from the Powerstone suite [21] and the Mälardalen WCET Benchmark suite [8] under three different SPM configurations, our approach achieves up to 21% and 43% improvements in WCET reduction over the ILP-based approach and the greedy approach, respectively.…”

Section: Introductionmentioning

confidence: 99%

WCET-aware data selection and allocation for scratchpad memory

Wan

Xue

2012

Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Syst

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In embedded systems, SPM (scratchpad memory) is an attractive alternative to cache memory due to its lower energy consumption and higher predictability of program execution. This paper studies the problem of placing variables of a program into an SPM such that its WCET (worst-case execution time) is minimized. We propose an efficient dynamic approach that comprises two novel heuristics. The first heuristic iteratively selects a most beneficial variable as an SPM resident candidate based on its impact on the k longest paths of the program. The second heuristic incrementally allocates each SPM resident candidate to the SPM based on graph coloring and acyclic graph orientation. We have evaluated our approach by comparing with an ILP-based approach and a longestpath-based greedy approach using the eight benchmarks selected from Powerstone and Mälardalen WCET Benchmark suites under three different SPM configurations. Our approach achieves up to 21% and 43% improvements in WCET reduction over the ILPbased approach and the greedy approach, respectively.

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WCET-Directed Dynamic Scratchpad Memory Allocation of Data

Cited by 77 publications

References 22 publications

An instruction scratchpad memory allocation for the precision timed architecture

An instruction scratchpad memory allocation for the precision timed architecture

Data cache organization for accurate timing analysis

WCET-aware data selection and allocation for scratchpad memory

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