Overlay performance with advanced ATHENA alignment strategies

This study characterizes the process influence on the alignment signal of deep trench (DT) process, and correlates product overlay with alignment results based on volume production data. The affecting processes include various steps of polysilicon thickness, nitride and oxide films, recess etch depth control, and resist thickness impact. Correlation also proves that the alignment signal plays an important role at the resulted long-term overlay stability. In order to improve the signal strength, further study focuses on the alignment optimization through mark design for deep trench process. The alignment marks evaluated include Scribe-lane Primary Marks (SPM) with difference process segmentations, short SPM marks and Versatile SPM marks. A good correlation is established between varying trench width or line width of mark segmentation and alignment signal strength. Comparison is also done for the signal strength between SPM mark and SSPM marks, between standard SPM mark and pure higher order marks.

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“…Some new mark types developed by ASML include Short SPM (SSPM), Versatile SPM (VSPM) 5 , and Narrow Short SPM (NSSM).…”

Section: Mark Type Evaluationmentioning

confidence: 99%

Segmented alignment mark optimization and signal strength enhancement for deep trench process

Cui

Goodwin

Haren

2004

Metrology, Inspection, and Process Control for Microlithography XVIII

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“…A reduction of ~10% of p2p residuals of the stacked VSPM mark is made by a change of alignment recipe from 5 th order Color Dynamic, to 7 th order Color Dynamic. Another 5% reduction in p2p residuals is obtained by a change of regular Color Dynamic recipe to a Smooth Color Dynamic [7] recipe.…”

Section: Average Signal Strength Improvementmentioning

confidence: 99%

“…It is noted here that these CMP effects to signal strength variation are only attributed to the difference in planarity of the Si wafer, and the polished layer(s) on top of this wafer. Control of alignment signal strength, and thus of alignment mark phase depth, is considered a main improvement possibility for overlay control [5,6,7]. A means to stabilize signal strength is to minimize the number of CMP steps involved for the copper floating marks.…”

Section: Figure 2 Cmp Transfer Function (Left) and Calculated A Substmentioning

confidence: 99%

Alignment robustness for 90 nm and 65 nm node through copper alignment mark integration optimization

Warrick¹,

Hinnen

Morton

et al. 2005

Optical Microlithography XVIII

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In this paper, methods for stacking ASML scribe lane alignment marks (SPM) and improving the mark performance at initial copper metal levels are discussed. The new mark designs and the theoretical reasons for mark design and/or integration change are presented. In previous joint publications between ASML and Freescale Semiconductor [1], improved overlay performance and alignment robustness for Back End Of Line (BEOL) layers by the application of stacked scribe lane marks (SPM) was presented.In this paper, further improvements are demonstrated through the use of optimized Versatile Scribe Lane Mark design (VSPM). With the application of stacked optimized VSPM-marks, the alignment signal strength of marks in the copper metal layer is increased compared to stacked SPM marks. The gains in signal strength stability, which is typical for stacked marks, as well as significantly reduced scribe lane usage, are also maintained. Through the placement of specially designed orthogonal scatter-bars in selected layers under the VSPM-marks, the alignment performance of initial inlaid metal layers is improved as well. The integration of these marks has been evaluated for the 90 nm and 65 nm technology nodes as part of a joint development program between the Crolles2 Alliance and ASML. A measured overlay improvement of ~10-15% was obtained by a strategy change from floating copper marks to stacked optimized VSPM marks.

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“…With the knowledge gained from joint development activities on on-product overlay, the increasing importance of synchronizing alignment mark design criteria, with alignment sensor hardware specifics was recognized [3,4,5,6]. Significant steps forward in this field were made, operating within the boundaries of the ATHENA TM sensor [4,6,8,15]. Improvements in overlay control have been achieved by evolution of alignment sensor hardware performance, system stability and mark design integration schemes.…”

Section: Introductionmentioning

confidence: 97%

Integration of a new alignment sensor for advanced technology nodes

Hinnen

Depre²,

Tanaka³

et al. 2007

SPIE Proceedings

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In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities. The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than 11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design. The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer alignment performance. On-product overlay results on manufacturing wafers were measured for three different process layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor. Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending on the layer measured. Finally the sensor's infrared wavelengths were used to demonstrate a robust alignment solution for wafers containing a semi-transparent hard-mask layer.

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Overlay performance with advanced ATHENA alignment strategies

Cited by 10 publications

References 8 publications

Segmented alignment mark optimization and signal strength enhancement for deep trench process

Segmented alignment mark optimization and signal strength enhancement for deep trench process

Alignment robustness for 90 nm and 65 nm node through copper alignment mark integration optimization

Integration of a new alignment sensor for advanced technology nodes

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