Overcoming wireload model uncertainty during physical design

Abstract

The advent of deep sub-micron technologies has created a number of problems for existing design methodologies. Most prominent among them is the problem of timing closure, whereby design time is dramatically increased due to iterations between gate-level synthesis and physical design. It is well known that the heart of this problem lies in the use of wireload models based on wirelength statistics from legacy designs. Some technology projections in [3] have suggested that wireload models will remain effective to block sizes on the order of 50k gates. This suggests that synthesis will not have to be changed much since this is approximately the maximum size for which logic synthesis is effective. However, our analyses on production designs show that the problem is not quite so straightforward, and the efficacy of synthesis using wireload models depends upon technology data as well as specific characteristics of the design. We analyze these effects and dependencies in detail in this paper, and draw some conclusions about the amount of physical information that is required for synthesis to be effective. Finally, we discuss the implications on hierarchical design flows, and propose a solution via physical prototyping.

A new LP based incremental timing driven placement for high performance designs

“…In recent publications, it has been shown that interconnect delay starts to dominate in deep submicron designs [19]. However, we should clarify that De j in formula (8) is not the commonly referred interconnect delay, which is the part of the gate delay resulting from driving the interconnect/wire capacitance.…”

Min-max placement for large-scale timing optimization

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At the 250nm technology node, interconnect delays account for over 40% of worst delays [12]. Transition to 130nm and below increases this figure, and hence the relative importance of timing-driven placement for VLSI.

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“…average) wirelength objective is the use of max instead of Σ 12. Quadratic placements work well in practice and can be produced very quickly; faster/better approaches are possible.…”

Verification of a complex SoC; the PRO/sup 3/ case-study

“…It is being argued however that for very deep submicron technologies it is not adequate any more (see for example [5]). The limitation arises from the fact that wire delays do not scaled with technology as much as gate delays, so for very fine geometries they are dominant.…”