Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

Abstract

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ∼1.2 μA μm along with a longer retention time (RT) of ∼1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

Dopingless 1T DRAM: Proposal, Design, and Analysis

“…We have calibrated the tunneling model by reproducing the results presented in [20] and also validated our simulation model using the results presented for a DRAM in [7]. For simplicity, we have not considered interface traps and tunneling through thin oxide in this work, similar to previous studies [6]- [9], [20]- [22]. We have taken the temperature as 300 K throughout this study.…”

“…Conventional MOSFET structures that utilize floating body capacitance and body charging effects have been proposed to be used as a 1T-DRAM [1], [2]. Tunnel field-effect transistors (TFET) because of their excellent subthreshold swing and weak temperature dependence are also being extensively explored for 1T-DRAM applications [3]- [9].…”

Analysis of Different Configurations of Si1-xGex for Double-Gate MOSFETs and Its Future Applications

“…It is done to accommodate performance with minimum power consumption and power dissipation. While doing so, we came across some limitations in form of Short Channel Effects (SCE), summarized in Table 1 [8][9][10][11]. To overcome them, new configuration doublegate MOSFETs shown in Figure 3 came into existence.…”

Enhancing multi-functionality of reconfigurable transistors by implementing high retention capacitorless dynamic memory

“…Although 1T-DRAM has been realized through novel architectures such as partially depleted Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field Effect Transistor (MOS-FET) [10], ultra-thin buried oxide (BOX) MOSFET [11,12], conventional double gate (DG) MOSFET [7], tunnel FETs [13][14][15][16][17], junctionless transistor [18][19][20][21], dopingless MOSFET [22,23], advanced random access memory (ARAM) [24] and its improved version (A2RAM) [25], zero-slope zero-impact ionization FET [26,27], raised source/drain MOSFET [28], electron-bridge channel structure [29] and vertical FET with body-on-gate structure [30]. In addition, material-device codesign has also been explored for 1T-DRAM such as GaAs junctionless transistor [31], SiGe impact ionisation MOS-FET [32], Ge/GaAs heterojunction tunnel FET [33] and SiGe quantum well structure [34].…”