2019 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) 2019
DOI: 10.1109/bcicts45179.2019.8972779
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Over 70-GHz 4.9-Vppdiff InP linear driver for next generation coherent optical communications

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Cited by 9 publications
(13 citation statements)
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“…The design presented in [5] uses a distributed amplifier topology and has a 47% higher bandwidth and a 18% lower power consumption than the proposed driver, however it has a 44% lower output voltage swing and a much lower linearity. The design in [6] (cascode topology) reaches a 42% higher bandwidth, but its linearity is much lower, its DC power consumption is 79% higher and it has a 32% lower output swing. The driver presented in [7] (distributed amplifier topology) is superior in terms of bandwidth (14% higher) and gain, however it is inferior in terms of output swing (31% lower), linearity and power consumption (64% higher).…”
Section: Comparison With the State Of The Artmentioning
confidence: 99%
See 1 more Smart Citation
“…The design presented in [5] uses a distributed amplifier topology and has a 47% higher bandwidth and a 18% lower power consumption than the proposed driver, however it has a 44% lower output voltage swing and a much lower linearity. The design in [6] (cascode topology) reaches a 42% higher bandwidth, but its linearity is much lower, its DC power consumption is 79% higher and it has a 32% lower output swing. The driver presented in [7] (distributed amplifier topology) is superior in terms of bandwidth (14% higher) and gain, however it is inferior in terms of output swing (31% lower), linearity and power consumption (64% higher).…”
Section: Comparison With the State Of The Artmentioning
confidence: 99%
“…However, it has a low bandwidth (40 GHz), a high power consumption (1 W) and only an average linearity, with a total harmonic distortion (THD) of 3.6% measured at 1 GHz. High bandwidths of 90 GHz and 86.8 GHz were achieved in [5] (using a distributed amplifier architecture) and [6] (using a cascode topology), respectively. Nevertheless, both designs show a low linearity, with a THD of 5% each (at 1 GHz and 10 GHz, respectively) as well as moderate output voltage swings (4 V pp,d and 4.9 V pp,d , respectively).…”
Section: Introductionmentioning
confidence: 99%
“…The output linear preamplifier and driver provide most of the voltage and power gain, an over 2-V ppd linear output swing, high equalization capabilities, and impedance matching on a 100diff load. To conjugate a very-high gain-bandwidth product and a largelinear-output swing, the driver architecture is based on a resistively degenerated paralleled-transistor cascode differential pair (see [18], [19]). Besides, a two-stage clock-path amplifier was used to ensure proper clock signal single-endedto-differential conversion.…”
Section: Introductionmentioning
confidence: 99%
“…The output swing of modulator drivers in CMOS is usually below 3 Vppd [2], [8], [9] as it is limited by the device breakdown voltage, which is technology-dependent. In recent years, drivers designed in technologies such as SiGe BiCMOS [10], [11], [12], [13], [14], [15], and InP DHBT [16], [17], [18] have been investigated because they have a collectorto-emitter breakdown voltage BV CEO over 1.5 V and f T / f MAX above 300 GHz. Those drivers achieve excellent performances: a low-frequency gain of more than 20 dB [2], [10], [13], a 3-dB bandwidth of over 67 GHz [10], [12], [13], [14], [18], and an output swing of beyond 4 Vppd [10], [11], [15] with a data rate of more than 90 Gb/s.…”
mentioning
confidence: 99%
“…A driver must have good linearity to support a high-order amplitude modulation format. The traditional drivers achieved good linearity but worsened rapidly if the input power exceeded a certain point [10], [11], [12], [13], [14], [15], [16], [17], [18]. The input power was limited to a small range in those drivers to keep good linearity and deliver the targeted output power.…”
mentioning
confidence: 99%