Output impedance requirements for DACs

Luschas, S.; Lee, H.-S.

doi:10.1109/iscas.2003.1205700

Cited by 61 publications

(36 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fig. 13 also shows a theoretical third-order harmonic distortion (HD3) calculation by considering only the output impedance of current cells [5], [12], [13]. It is expressed as where R L,d = 50 Ω is the differential resistance of the DAC output loads, M = 32 is the total number of M-DAC current cells, and Z o is the output impedance of an M-DAC current cell.…”

Section: Resultsmentioning

confidence: 99%

“…The SFDR decreases rapidly with increasing input frequency. The sources of dynamic nonlinearity are numerous and complex, including code-dependent switching transients [6], [7] and the capacitive output impedance of the current cells [5], [12], [13]. The return-to-zero (RZ) technique has been proposed to improve the DAC dynamic performance [6], [8], [9].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero

Tseng

Chu

2011

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

Abstract-A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.Index Terms-Current steering, digital-to-analog converter (DAC), digital random return-to-zero (DRRZ), return-tozero (RZ).

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero

Tseng

Chu

2011

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…The dynamic performance of the DAC is limited by five main reasons. Firstly, the output impedance of the current cell is a function of its capacitance, which is non-linear and dominates at high frequencies [14][15][16][17]. The harmonic distortion of the DAC is given by…”

Section: Characteristics Of Nyquist Dacsmentioning

confidence: 99%

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

View full text Add to dashboard Cite

Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

show abstract

“…As illustrated in Fig. 2.4, there is normally a relationship between resolution and frequency in digital-to-analog converters [19][20][21][22][23]: with higher frequencies, the linearity decreases [20,24].…”

Section: Current-steering Digital-to-analog Convertersmentioning

confidence: 99%

On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters

Sadeghifar¹

2015

Linköping Studies in Science and Technology. Thesis

View full text Add to dashboard Cite

High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatorypulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have highenergy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency upconversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element.In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatorypulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work.Σ∆ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal's number of bits, still maintain the same resolution. By utilizing the Σ∆ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing Σ∆ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the Σ∆ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement.Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with Σ∆ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only t...

show abstract

Output impedance requirements for DACs

Cited by 61 publications

References 3 publications

A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero

A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters

Contact Info

Product

Resources

About