Outlook for Nanoelectronic Devices

Abstract

practical allowable power dissipation of approximately 100 W/cm 2 , and not by their size. The conclusion of this work is that MOSFET technology scaled to its practical limit in terms of size and power density will asymptotically reach the theoretical limits of scaling for charge-based devices.Most of the proposed beyond-CMOS replacement devices are very different from their CMOS counterparts, and often pass computational state variables (or tokens) other than charge. Alternative state variables include collective or single spins, excitons, plasmons, photons, magnetic domains, qubits, and various ordering parameters observed in solid state phase dynamics (e.g., ferromagnetic state). With the multiplicity of computational state variables and physical mechanisms employed in the new structures, it is necessary to find new ways to benchmark the technologies effectively. This requires a combination of existing benchmarks used for CMOS and new benchmarks which take into account the idiosyncrasies of the new device behavior. Even more challenging is to extend this process to consider new circuits and architectures beyond the Boolean architecture used by CMOS today. Architectural Requirements for a Competitive Logic DeviceCircuit designers and architects depend on the logic switch to exhibit specific desired characteristics to realize a wide range of applications, including [5]:

Science and research policy at the end of Moore’s law

“…Further, as highlighted in the move from single-to multi-core processors, downstream technology shifts require coordination up and down the computing technology stack. Specifically, an entirely new computing element will possibly require changes in state variable, material, device, data representation, architecture and programming methodology 53 . The current environment simply lacks the sort of coordinating institutions that guided previous technology shifts (large corporate research laboratories, for example, in the case of the shifts from vacuum tubes to transistors to integrated circuits).…”

Fulfilling the promise of the materials genome initiative with high-throughput experimental methodologies

“…Another emerging device area is 2D materials 86 such as transition metal dichalcogenides, 87 ferroelectric materials for negative-gate-capacitance field effect transistors, 88 traditional field effect transistors, ferroelectric-dynamic random access memory cells, 89 resistive random access memory cells, 86 Mott field effect transistors, 86 and chalcogenidebased memories, 86 where specific materials properties are leveraged in conjunction with device behavior to enable transistor scaling of novel memory devices. Applying HTE methodologies in the aforementioned areas requires the means to process the materials in dimensionally and compositionally controlled thin film stacks, using relevant processing tools such as sputtering or ALD, and appropriate thermal budgets.…”

Field‐ and irradiation‐induced phenomena in memristive nanomaterials

“…Several books have as well been published on fundamentals and potential applications of memristive devices [18][19][20][21], however, the choice of materials (electrodes, switching layer) and of their deposition technology remains a key problem that must be solved for each specific application.…”