Oscillator without a combinatorial loop and its threat to FPGA in data centre

Abstract

Virtual field‐programmable gate array (FPGA) is an emerging technology to put multiple users in the same FPGA fabric with logical isolation. Security researchers have studied new threats in virtual FPGA and proposed attacks on the logical isolation by exploiting analogue natures of FPGA. These attacks use an oscillator comprising a combinatorial loop to have access to the analogue domain using digital components only. Interestingly, the system in the field prohibits a combinatorial loop by a design rule check. In this Letter, the authors study if prohibiting a combinatorial loop is sufficient to thwart the conventional attacks. They negatively answer the question by showing oscillators without a combinatorial loop. They also show how to detect and reject the proposed oscillators by a design rule check.

Reading Between the Dies: Cross-SLR Covert Channels on Multi-Tenant Cloud FPGAs

“…As AWS prohibits combinatorial loops from user designs [2], we use alternative RO designs introduced recently [13], [33]. Although traditional ROs use only combinational logic through lookup-tables (LUT-RO), by replacing a buffer stage with a latch (LD-RO) or a flip-flop (FF-RO), one can overcome restrictions placed by cloud providers today.…”

“…Simply banning combinatorial loops [14], [15], [24], [36], [47] has proven to be insufficient, since both Time-to-Digital Converters (TDCs) [30], [31], [47] and alternative ring oscillator (RO) designs [13], [33] can bypass design checks implemented by some cloud FPGA providers, with others not deploying any such checks at all. These alternative designs could be detected in some cases, by banning latches [13], [15], [33] and only allowing global clocks to drive flip-flops [13], [33]. However, alternative TDC designs without latches, and gated global clocks through clock enable pins may still be able to circumvent these proposed checks.…”

“…Ring Oscillators (ROs) and Time-to-Digital Converters (TDCs) have also been used to conduct intra-chip [25], [30], [47] and inter-chip [31] side-channel attacks. Although some cloud providers, such as Amazon AWS, detect ROs and prohibit their use [2], recent work [13], [33] has demonstrated that alternative RO designs can bypass cloud restrictions. Neither of the two works conducted a practical attack: Sugawara et al merely proved that instantiation of alternative ROs was possible on AWS [33], while Giechaskiel et al characterized long-wire leakage on local and cloud FPGAs leveraging ROs that are likewise not caught by the design rule checks of the cloud providers [13].…”

“…Although some cloud providers, such as Amazon AWS, detect ROs and prohibit their use [2], recent work [13], [33] has demonstrated that alternative RO designs can bypass cloud restrictions. Neither of the two works conducted a practical attack: Sugawara et al merely proved that instantiation of alternative ROs was possible on AWS [33], while Giechaskiel et al characterized long-wire leakage on local and cloud FPGAs leveraging ROs that are likewise not caught by the design rule checks of the cloud providers [13]. Long-wire leakage requires transmitter and receiver long wires to be adjacent, whereas we have constructed the first cloud-based covert channel, which remains fast and accurate despite physical isolation to separate SLRs.…”

C3APSULe: Cross-FPGA Covert-Channel Attacks through Power Supply Unit Leakage

“…It should be noted that some cloud providers such as Amazon Web Services (AWS) place restrictions on the types of circuits that can be instantiated on their FPGAs, and prohibit combinatorial loops including ring oscillators. Although in this work we primarily use conventional ring oscillators, Section V-E shows that they can be easily replaced by alternate designs proposed in recent work [8], [10], [11], [34], which bypass cloud countermeasures.…”