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2014 IEEE International Reliability Physics Symposium 2014
“…According to previous reports [12, 28, 33], the parallel shift in I D – V G curves is attributed to the gradual accumulation of trapped charges in the gate stack, while the slope degradation in I D – V G curves is the result of interface trap generation. Since trapped charges can be de-trapped by electrical means, but generation of interface traps is irreversible, minimizing interface trap generation is extremely important for improving the endurance properties [28]. The interface traps generated by P/E cycling (Δ N it ) can be described using Eq.…”
Section: Resultsmentioning
confidence: 65%
“…However, the gate leakage current for the FeFET with the additional crystalline ZrO 2 seed layer almost does not change up to 5 × 10 2 cycles, and it is always smaller than that for the FeFET without the additional crystalline ZrO 2 seed layer. It is reported that the increase in the gate leakage current might be related to the generated interface traps [28]. The reduction in the gate leakage current with cycling for the FeFET with the additional crystalline ZrO 2 seed layer would be attributed to the suppression of interface trap generation.Fig.…”
Section: Resultsmentioning
confidence: 96%
“…For the FeFET without the additional crystalline ZrO 2 seed layer, both significant shift and slope degradation in the I D – V G curves are observed from the early stages of P/E cycling, and the I D – V G curves in the erased states exhibit more slope degradation compared with the program states. For the FeFET with the additional crystalline ZrO 2 seed layer, although the I D – V G curves in erased states exhibit an obvious positive shift during the early stages of P/E cycling that is attributed to the “wake up” effect [13, 28–32], no obvious shift of I D – V G curves in the program states is observed up to 1 × 10 3 cycles. Moreover, for the FeFET with the additional crystalline ZrO 2 seed layer, the I D – V G curves in both erased and program states exhibit only a slight slope degradation up to 1 × 10 3 cycles.Fig.…”
The HfO
2
-based ferroelectric field effect transistor (FeFET) with a metal/ferroelectric/insulator/semiconductor (MFIS) gate stack is currently being considered as a possible candidate for high-density and fast write speed non-volatile memory. Although the retention performance of the HfO
2
-based FeFET with a MFIS gate stack could satisfy the requirements for practical applications, its memory window (MW) and reliability with respect to endurance should be further improved. This work investigates the advantage of employing ZrO
2
seed layers on the MW, retention, and endurance of the Hf
0.5
Zr
0.5
O
2
(HZO)-based FeFETs with MFIS gate stacks, by using fast voltage pulse measurements. It is found that the HZO-based FeFET with a ZrO
2
seed layer shows a larger initial and 10-year extrapolated MW, as well as improved endurance performance compared with the HZO-based FeFET without the ZrO
2
seed layer. The results indicate that employing of a direct crystalline high-k/Si gate stack would further improve the MW and reliability of the HfO
2
-based FeFETs.
“…According to previous reports [12, 28, 33], the parallel shift in I D – V G curves is attributed to the gradual accumulation of trapped charges in the gate stack, while the slope degradation in I D – V G curves is the result of interface trap generation. Since trapped charges can be de-trapped by electrical means, but generation of interface traps is irreversible, minimizing interface trap generation is extremely important for improving the endurance properties [28]. The interface traps generated by P/E cycling (Δ N it ) can be described using Eq.…”
Section: Resultsmentioning
confidence: 65%
“…However, the gate leakage current for the FeFET with the additional crystalline ZrO 2 seed layer almost does not change up to 5 × 10 2 cycles, and it is always smaller than that for the FeFET without the additional crystalline ZrO 2 seed layer. It is reported that the increase in the gate leakage current might be related to the generated interface traps [28]. The reduction in the gate leakage current with cycling for the FeFET with the additional crystalline ZrO 2 seed layer would be attributed to the suppression of interface trap generation.Fig.…”
Section: Resultsmentioning
confidence: 96%
“…For the FeFET without the additional crystalline ZrO 2 seed layer, both significant shift and slope degradation in the I D – V G curves are observed from the early stages of P/E cycling, and the I D – V G curves in the erased states exhibit more slope degradation compared with the program states. For the FeFET with the additional crystalline ZrO 2 seed layer, although the I D – V G curves in erased states exhibit an obvious positive shift during the early stages of P/E cycling that is attributed to the “wake up” effect [13, 28–32], no obvious shift of I D – V G curves in the program states is observed up to 1 × 10 3 cycles. Moreover, for the FeFET with the additional crystalline ZrO 2 seed layer, the I D – V G curves in both erased and program states exhibit only a slight slope degradation up to 1 × 10 3 cycles.Fig.…”
The HfO
2
-based ferroelectric field effect transistor (FeFET) with a metal/ferroelectric/insulator/semiconductor (MFIS) gate stack is currently being considered as a possible candidate for high-density and fast write speed non-volatile memory. Although the retention performance of the HfO
2
-based FeFET with a MFIS gate stack could satisfy the requirements for practical applications, its memory window (MW) and reliability with respect to endurance should be further improved. This work investigates the advantage of employing ZrO
2
seed layers on the MW, retention, and endurance of the Hf
0.5
Zr
0.5
O
2
(HZO)-based FeFETs with MFIS gate stacks, by using fast voltage pulse measurements. It is found that the HZO-based FeFET with a ZrO
2
seed layer shows a larger initial and 10-year extrapolated MW, as well as improved endurance performance compared with the HZO-based FeFET without the ZrO
2
seed layer. The results indicate that employing of a direct crystalline high-k/Si gate stack would further improve the MW and reliability of the HfO
2
-based FeFETs.
“…As seen in Figure d, however, the endurance property was limited to 10 4 cycles at this stage. This can be improved by engineering the stacks and the operating conditions . In fact, with very high density of bits, the endurance of 10 4 could be sufficient for many applications .…”
The recent progress in ferroelectricity and antiferroelectricity in HfO2-based thin films is reported. Most ferroelectric thin film research focuses on perovskite structure materials, such as Pb(Zr,Ti)O3, BaTiO3, and SrBi2Ta2O9, which are considered to be feasible candidate materials for non-volatile semiconductor memory devices. However, these conventional ferroelectrics suffer from various problems including poor Si-compatibility, environmental issues related to Pb, large physical thickness, low resistance to hydrogen, and small bandgap. In 2011, ferroelectricity in Si-doped HfO2 thin films was first reported. Various dopants, such as Si, Zr, Al, Y, Gd, Sr, and La can induce ferro-electricity or antiferroelectricity in thin HfO2 films. They have large remanent polarization of up to 45 μC cm(-2), and their coercive field (≈1-2 MV cm(-1)) is larger than conventional ferroelectric films by approximately one order of magnitude. Furthermore, they can be extremely thin (<10 nm) and have a large bandgap (>5 eV). These differences are believed to overcome the barriers of conventional ferroelectrics in memory applications, including ferroelectric field-effect-transistors and three-dimensional capacitors. Moreover, the coupling of electric and thermal properties of the antiferroelectric thin films is expected to be useful for various applications, including energy harvesting/storage, solid-state-cooling, and infrared sensors.
“…a continuous change of the polarization state, results in a degradation and consequent reduction of the MW. In contrast the unipolar stress does not influence the MW significantly [59,81,82]. Leakage current defect spectroscopy proved that independent of the polarity of the unipolar stress pulses, both leakage current and memory window stayed constant.…”
Abstract. The discovery of ferroelectric properties of binary oxides revitalized the interest in ferroelectrics and bridged the scaling gap between the state-of-the-art semiconductor technology and ferroelectric memories. However, before hitting the markets, the origin of ferroelectricity and in-depth studies of device characteristics are needed. Establishing a correlation between the performance of the device and underlying physical mechanisms is the first step toward understanding the device and engineering guidelines for a novel, superior device. Therefore, in this paper a holistic modeling approaches which lead to a better understanding of ferroelectric memories based on hafnium and zirconium oxide is addressed. Starting from describing the stabilization of the ferroelectric phase within the binary oxides via physical modeling the physical mechanisms of the ferroelectric devices are reviewed. Besides, limitations and modeling of the multi-level operation and switching kinetics of ultimately scaled devices as well as the necessity for Landau-Khalatnikov approach are discussed. Furthermore, a device level model of ferroelectric memory devices that can be used to study the array implementation and their operational schemes are addressed. Finally, a circuit model of the ferroelectric memory device is presented and potential further applications of ferroelectric devices are outlined.
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