Optimum transistor sizing for low-power subthreshold standard cell designs

Grimminger, Florian; Fischer, Georg; Weigel, Robert; Kissinger, Dietmar

doi:10.1109/iscdg.2012.6360033

Cited by 3 publications

(2 citation statements)

References 3 publications

(3 reference statements)

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“…So in order to overcome such disadvantages and trade-offs, Sub threshold conduction arrives, in which the circuit start conduction within the sub threshold region before input voltage reaches the threshold voltage. The relationship between W/L and source drain current is equally simple [9]. As the channel width increases, more carriers are available to conduct current.…”

Section: Subthreshold Conductionmentioning

confidence: 99%

Design of Efficient adder Circuits in Sub Threshold Region

Shajini¹,

J²

2017

International Journal of Innovative Research in Electrical, Ele

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Sub threshold (leakage or cutoff) currents are a necessary in traditional VLSI design methodologies. Ultralow power applications such as micro-sensor networks, pacemakers, and many portable devices require extreme energy constraints for longer battery life. Increasing the battery life can provide a competitive advantage in the marketplace. Traditionally, reducing the power supply voltage is regarded as the most effective means of reducing power consumption. Therefore, digital circuits operating in the sub threshold region offer a promising solution for emerging portable applications that require tremendously low energy consumption. The proposed work is to compare the performance of various CMOS circuits such as inverter, Half adder, Full adder between conventional conduction and sub threshold conduction in terms of power and delay. As a result the circuits under sub threshold conduction is efficient than conventional because power of sub threshold circuit is less than conventional circuit. The circuits are design using tanner tool.

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Section: Subthreshold Conductionmentioning

confidence: 99%

Design of Efficient adder Circuits in Sub Threshold Region

Shajini¹,

J²

2017

International Journal of Innovative Research in Electrical, Ele

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“…For an optimal dimensioning, the technique presented in [4] and [5] is applied. The reverse short channel effect is ex ploited in order to modulate the threshold voltage for an optimal subthreshold operation.…”

Section: Implementation With Subthreshold Logicmentioning

confidence: 99%

Asynchronous subthreshold CMOS event detector for wireless BAN sensor nodes

Grimminger

Kowalczyk

Unterassinger

et al. 2014

2014 IEEE Topical Conference on Biomedical Wireless Technologies, Networks, and Sensing Systems (BioWireleSS)

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This work presents the implementation of an asynchronous event detector circuit by applying subthreshold standard cells. The presented circuit operates in an on-chip power management unit (PMU) of a wireless sensor node. Such an application demands an ultra-low power architecture for an increased overall lifetime of the sensor node. The asynchronous circuit architecture and its subthreshold logic implementation both significantly reduce the leakage power dissipation by factor three. The presented event detector is realized in a 130 nm CMOS process with regular transistors operating from a 200 mV supply voltage.

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