Optimizing time-to-digital converter architecture for successive approximation time measurements

Kościelnik, Dariusz; Miśkowicz, Marek; Szyduczyński, Jakub; Rzepka, Dominik

doi:10.1109/nometdc.2013.6658239

Cited by 7 publications

(15 citation statements)

References 13 publications

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“…Also, this system exhibits a 474-ps resolution, which is well behind even delay line implementations available in 2016 (17 ps in [32]). References [33] and [34] also present a linear (unrolled) implementation of the SA-TDC, achieving 25 and 12.5 ps, respectively, on 180 nm.…”

Section: B Successive Approximation Tdcmentioning

confidence: 99%

A Review of New Time-to-Digital Conversion Techniques

Tancock

Arabul

Dahnoun

2019

IEEE Trans. Instrum. Meas.

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Time-to-digital converters (TDCs) are vital components in time and distance measurement and frequency-locking applications. There are many architectures for implementing TDCs, from simple counter TDCs to hybrid multi-level TDCs, which use many techniques in tandem. This article completes the review literature of TDCs by describing new architectures along with their benefits and tradeoffs, as well as the terminology and performance metrics that must be considered when choosing a TDC. It describes their implementation from the gate level upward and how it is affected by the fabric of the device [field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)] and suggests suitable use cases for the various techniques. Based on the results achieved in the current literature, we make recommendations on the appropriate architecture for a given task based on the number of channels and precision required, as well as the target fabric.

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Section: B Successive Approximation Tdcmentioning

confidence: 99%

A Review of New Time-to-Digital Conversion Techniques

Tancock

Arabul

Dahnoun

2019

IEEE Trans. Instrum. Meas.

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“…The successive approximation scheme belongs to fundamental and most successful methods of analog-to-digital conversion that has been implemented commercially for decades and is still used nowadays. Usually, the successive approximation is realized by oscillating or monotone algorithm [ 22 ]. Most ADCs for voltage input use the oscillating successive approximation (e.g., well-known ADC with charge redistribution [ 43 ]).…”

Section: Schemes Of Successive Approximation In Analog-to-digital mentioning

confidence: 99%

“…By analogy to analog-to-digital converters, they can be classified into Nyquist-rate TDCs and oversampled TDCs [ 16 ]. Nyquist-rate TDCs include counter TDCs, delay line and Vernier line TDCs [ 10 , 12 , 21 ], TDCs with interpolation, pulse-shrinking or pulsestretching, successive approximation TDCs [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 ], flash and pipelined TDCs [ 1 , 2 ]. Noise-shaping TDCs are aimed to suppress the quantization noise using system-level techniques such as Sigma-Delta modulation by moving most of in-band quantization noise outside the signal band in order to achieve a large signal-to-noise ratio (SNR) and improve effective TDC resolution.…”

Section: Introductionmentioning

confidence: 99%

“…This paper focuses on time-to-digital converters based on successive approximation (SA-TDCs—Successive Approximation TDCs) [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 ]. The aim of the paper is to give a tutorial on successive approximation TDCs (SA-TDCs) on one hand, and to make the contribution to optimization of SA-TDC design on the other.…”

Section: Introductionmentioning

confidence: 99%

“…The careful analysis shows that the reduction of complexity for 8-bit SA-TDC is around 20–30%, while for 12 bits respectively almost 50%. The present study is an extension of the conference papers [ 22 , 23 , 24 ].…”

Section: Introductionmentioning

confidence: 99%

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A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements

Szyduczyński

Kościelnik

Miśkowicz

2019

Sensors

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The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs—Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on successive approximation TDCs (SA-TDCs) on the one hand, and to make the contribution to optimization of SA-TDC design on the other. The proposed design optimization consists essentially in reduction of circuit complexity and die area, as well as in improving converter performance. The main paper contribution is the concept of reducing SA-TDC complexity by removing one of two sets of delay lines in the feedforward architecture at the price of simple output decoding. For 12 bits of resolution, the complexity reduction is close to 50%. Furthermore, the paper presents the implementation of 8-bit SA-TDC in 180 nm CMOS technology with a quantization step 25 ps obtained by asymmetrical design of pair of inverters and symmetrized multiplexer control.

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