Optimizing the load transient response of the buck converter

Redl, R.; Erisman, B.P.; Zansky, Z.

doi:10.1109/apec.1998.647687

Cited by 127 publications

(73 citation statements)

References 3 publications

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“…From Fig. 4 it can be seen that, assuming , the excursion due to a load current step is (16) Equation (16) shows that the output voltage step is directly proportional to the output current step, with proportionality constant which is a linear combination of the output capacitor ESR and the delay of the controller. Thus, using the reasoning behind the optimal voltage positioning technique, we can design the controller to always position at (17) where (18) This extension is particularly important for capacitor technologies with small , such as ceramic capacitors, where the term corresponding to controller delay may dominate.…”

Section: B Implementation Of Optimal Voltage Positioningmentioning

confidence: 99%

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Architecture and IC implementation of a digital VRM controller

Peterchev

Xiao

Sanders

2003

IEEE Trans. Power Electron.

335

117

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Abstract-This paper develops the architecture of a digital PWM controller for application in multiphase voltage regulation modules (VRMs). In this context, passive current sharing and VRM transient response with nonzero controller delay are analyzed. A scheme for sensing a combination of the VRM output voltage and output current with a single low-resolution window analog-to-digital converter (ADC) is proposed. The architecture and IC implementation of a digital PWM (DPWM) generation module, using a ring-oscillator-multiplexer scheme, is discussed. Experimental results from a prototype VRM and a partial controller IC implementation are presented.

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Section: B Implementation Of Optimal Voltage Positioningmentioning

confidence: 99%

“…The idea is to always position at , where is the reference voltage, instead of driving it to [16]. In that case, the converter behaves as a voltage source with value and output impedance that is always real and equal to .…”

Section: B Implementation Of Optimal Voltage Positioningmentioning

confidence: 99%

Architecture and IC implementation of a digital VRM controller

Peterchev

Xiao

Sanders

2003

IEEE Trans. Power Electron.

335

117

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“…As described in [2], the minimum achievable output voltage transient appearing at the onset of an overload is:…”

Section: Output Capacitor Design Criteriamentioning

confidence: 99%

Two-Domains Control of a Buck Converter

et al. 2017

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In the design of a power converter, the maximum output voltage transient under load change is one of the main drivers. The ECSS-E-ST-20C imposes specific requirements on the power quality of a regulated bus, which result most of the time in the use of a large capacitor bank to cope with the linear loop dynamics. Moreover, this sometimes results in slow dynamic response.In this paper a combined linear and non-linear control applied to a buck converter is proposed. This control technique enhances the transient performance with a faster recovery time and allows smaller output filter capacitors to be used. The proposed control is a combination of a linear control based on a conductance control principle, and a non-linear control, which intervenes only during transients. The latter is based on the detection of the output voltage variation and on the immediate application of maximum or minimum inductor current, as consequence of voltage undershoot or overshoot. Once the controlled output voltage is within the allowed range, the linear control takes back the voltage regulation control.The buck converter is chosen as a reference topology since most of the current solar array regulators (SARs) use a buck or super buck topology. Most Battery Discharge Regulators (BDRs) are also based on buckderived topologies.This concept can find application in the three-domain regulated bus control.

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“…Thus, the method resistive, or to meet another desired specification, over a used poses the same practical challenges as inductor sensing. wide frequency range, by processing the output current Ideally, a VRM system would include an output current information [2].…”

Section: Introductionmentioning

confidence: 99%

“…Adaptive frequency range, especially as C0 is decreased to reduce voltage positioning (AVP), also known as load-line regula-costs. In order to enhance load-line tracking without pushing tion, was adopted as an effective technique to reduce the the feedback bandwidth close to instability, output current amount of capacitance at the output [2]. This technique feedforward was proposed [7].…”

Section: Introductionmentioning

confidence: 99%