Architecture and IC implementation of a digital VRM controller

Abstract

Abstract-This paper develops the architecture of a digital PWM controller for application in multiphase voltage regulation modules (VRMs). In this context, passive current sharing and VRM transient response with nonzero controller delay are analyzed. A scheme for sensing a combination of the VRM output voltage and output current with a single low-resolution window analog-to-digital converter (ADC) is proposed. The architecture and IC implementation of a digital PWM (DPWM) generation module, using a ring-oscillator-multiplexer scheme, is discussed. Experimental results from a prototype VRM and a partial controller IC implementation are presented.

Effects of nonidealities in switching frequency modulation techniques: Application to coupled interleaved multicellular parallel converters

“…Duty-cycle mismatch can be caused by different factors. The most relevant are switch driver imperfections and impedance mismatch among converter phases [7,10]. The effect of driver imperfections, such as rise/fall times, or unequal switching behavior of devices is only noticeable for central switching frequencies in the range of MHz.…”

“…Regarding the second reason, mismatch of parasitic impedances among phases produce a current unbalance [7]. Therefore, a duty cycle deviation from the ideal case must be introduced to equally share currents among phases, according to (6),…”

“…For these reasons, CIMPC topology is widely used in applications where outstanding dynamic performance is required, such in Voltage Regulator Modules (VRM) [7]. However, in this kind of converters, which are operated with interleaving, an accurate control and modulation are required in order to ensure a proper current balancing among each single switching cell of the converter [8].…”

“…In order to adjust the current distribution, it is necessary to vary the duty cycle in each phase from the ideal duty cycle. The dispersion in duty cycle values is identified as the most important parameter in attenuation degradation when pure interleaving is applied [7,10]. This paper explores the feasibility of application of VDFM to CIMPC.…”

Digital loss-minimizing multimode synchronous buck converter control

“…This method requires only coarse sampling of the scheduling variable (e.g., the output current) at a rate equal to the switching frequency, and low-bandwidth sensing of a single quantity characterizing the converter performance (e.g., power loss, input current, or temperature). This method is particularly well-suited for a digital controller implementation [7], since it uses low rate computations and data storage, thus not requiring analog-todigital sampling rates beyond the converter switching frequency, which is typically in the range of hundreds of kHz.…”