Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis

Abstract

Injection-locked frequency dividers (ILFDs) are versatile analog circuit blocks used, for example, within phase-locked loops (PLLs). With respect to their digital counterparts, they have the advantages of a low power consumption and division ratios greater than two. The price for these advantages is believed to be a limited locking range. Here we show that this is not the case; indeed, by combining nonlinear systems theory (bifurcation analysis) with optimization techniques, we have significantly increased the locking range of a classical (LC oscillator-based) injection-locked frequency divider, predicting a locking range that is about twenty times greater than what has been reported in the literature to date. The wider locking range predicted by the theory has been confirmed by SPICE simulations.

Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis

“…Using the results of [8], we have selected values of Q and G which yield moderately wide divide-by-2 and divideby-4 regions, as shown in Fig. 2.…”

“…1(c) at the origin [8]. To simplify the analysis, we assume that the modulation of the tail resistor (R t ) is mainly manifested as a variation of the parameter a.…”

“…Therefore, replacing transistor M 5 by a voltage-controlled resistor, we model the circuit using the simplified parametric model in Fig. 1(b) [8]. This simplified circuit consists of an RLC tank in parallel with a nonlinear resistor; it has the following state equations:…”

“…However, despite important analytical studies [2]- [3], there is still no robust design methodology to predict the oscillator locking range a priori as a function of the design parameters. A low frequency SPICE validation of a new idea [8] to predict the locking range is considered in this paper and our future work will focus on an integrated circuit implementation at microwave frequencies.…”

An LC CMOS injection-locked frequency divider for divide-by-two and divide-by-three operation

“…The use of digital frequency dividers is constrained at high frequencies by their high power consumption, which increases rapidly with frequency [11]. As an alternative to digital dividers, analog FDs are attractive because of their lower power consumption and high speed and frequency capabilities [12]. Compared to CML and Miller dividers, the power consumption of an ILFD does not increase significantly with frequency.…”