Optimizing systolic networks by fitting diagonals

Surós, Rina; Montagne, Eurípides

doi:10.1016/0167-8191(87)90049-4

Cited by 12 publications

(1 citation statement)

References 3 publications

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“…By making the design of the processors more complex, it seems possible (e.g. Suros and Montagne [21]) to coalesce the three processors per stage into two, both of them operating 100 percent of the time. However, the present design uses the non-operation time of the processors to compute immediately successive blocks of data without interruption or data mixing.…”

Section: Methodsmentioning

confidence: 99%

FFT computation with systolic arrays, a new architecture

Boriakoff

1994

IEEE Trans. Circuits Syst. II

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The use of the Cooley-Tukey algorithm for computing the 1-d FFT lends itself to a particular matrix factorization which suggests direct implementation by lmearly-connected systolic arrays. Here we present a new systolic architecture that embodies this algorithm. This implementation requires a smaller number of processors and a smaller number of memory cells than other recent implementations, as well as having all the advantages of systolic arrays. For the implementation of the decimation-in-frequency case, word-serial data input allows continuous real-time operation without the need of a serial-toparallel conversion device. No control or data stream switching is necessary. Computer simulation of this architecture was done in the context of a 1024 point D m witb a fixed point processor, and CMOS processor implementation has started. Index Terms-Fast Fourier "sform, on-line processing, systolic arrays, VLSI.

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Section: Methodsmentioning

confidence: 99%