FFT computation with systolic arrays, a new architecture

Boriakoff, V.

doi:10.1109/82.285710

Cited by 32 publications

(8 citation statements)

References 16 publications

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“…In the Viterbi decoding process, any two updated path metrics at a state of stage , and , are compared using subtraction. It has been shown in [9], [10] that if , the comparison can be evaluated as without any ambiguity. Hence, the updated path metrics at any state of a stage can be computed modulo .…”

Section: Modulo Arithmetic For Acsmentioning

confidence: 98%

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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Guo

Ahmad

Swamy

et al. 2005

IEEE Trans. Circuits Syst. I

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In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware.Index Terms-Adaptive Viterbi decoder, field-programmable gate array (FPGA) implementation, low-power design, systolic array architecture.

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Section: Modulo Arithmetic For Acsmentioning

confidence: 98%

“…At the start, the path metric, the survivor state, and the survivor information are initialized as (7) (8) for otherwise (9) Let represent the survived states at the th stage. Then, and can be expressed as otherwise (10)…”

Section: B Updating Of Path Metricsmentioning

confidence: 99%

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Guo

Ahmad

Swamy

et al. 2005

IEEE Trans. Circuits Syst. I

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“…Systolic designs represent a popular architectural paradigm for efficient VLSI implementation of computationally intensive digital signal processing (DSP) applications, not only due to the simplicity of their design using repetitive identical processing elements (PEs) with regular and local interconnections, but also for their potential of using a high level of pipelining in a small chip area with low power consumption inherent with the structure [6]. The radix-2 fast Fourier transform (FFT)-based structures [7], [8] have time complexity and involve multiply accumulators along with delay elements for -point transform, but they can be used only for power-of-two transform lengths. The radix-4 FFT-based structure of [9] offers still lower hardware complexity over the radix-2 FFT-based structures, but can be used for power-of-4 [9] need to perform fewer arithmetic operations, but, due to their irregular signal-flow graphs, they involve complicated routing, which leads to lower VLSI packing density, more power consumption, and more design time.…”

Section: Introductionmentioning

confidence: 99%

Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation

Meher

2006

IEEE Trans. Circuits Syst. II

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A reduced-complexity algorithm is presented for computation of the discrete Fourier transform, where -point transform is computed from eight number of nearly ( 8)-point circular-convolution-like operations. A systolic architecture is also derived for very large-scale integration circuit implementation of the proposed algorithm. The proposed architecture is fully pipelined and contains regular and simple locally connected processing elements. It is devoid of complex control structure and is scalable for higher transform lengths. It is observed that the proposed systolic structure involves either less or nearly the same hardware-complexity compared with the corresponding existing systolic structures. In addition, it offers eight times more throughput and significantly low latency compared with the others.Index Terms-Digital signal processing chip, discrete Fourier transform (DFT), systolic array, VLSI.

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“…As the total size of tables can be found by summing all the costs of non-leaf nodes, the cost of a binary tree is defined as (4) where is the set of all nodes and is the set of leaves.…”

Section: Thanmentioning

confidence: 99%

Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing

Lee

Park

2007

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents an area-efficient algorithm for the pipelined processing of fast Fourier transform (FFT). The proposed algorithm is to decompose a discrete Fourier transform (DFT) into two balanced sub-DFTs in order to minimize the total number of twiddle factors to be stored into tables. The radix in the proposed decomposition is adaptively changed according to the remaining transform length to make the transform lengths of sub-DFTs resulting from the decomposition as close as possible. An 8192-point pipelined FFT processor designed for digital video broadcasting-terrestrial (DVB-T) systems saves 33% of general multipliers and 23% of the total size of twiddle factor tables compared to a conventional pipelined FFT processor based on the radix-2 2 algorithm. In addition to the decomposition, several implementation techniques are proposed to reduce area, such as a simple index generator of twiddle factor and add/subtract units combined with the two's complement operation.Index Terms-Balanced binary-tree decomposition, digital video broadcasting-terrestrial (DVB-T), fast Fourier transform (FFT), orthogonal frequency division multiplexing (OFDM), pipelined processing.

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FFT computation with systolic arrays, a new architecture

Cited by 32 publications

References 16 publications

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation

Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing

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