Optimizing power-accuracy trade-off in approximate adders

Celia, D.; Vasudevan, V.; Chandrachoodan, Nitin

doi:10.23919/date.2018.8342248

“…First, we consider the direct form I realization of an 18-tap low pass FIR filter, where the accurate adders are replaced with approximate adders. Among the LPAAs, AMA-5 [4], LOA [5], ETA-I [6], Truncation adder and MA [7] have been observed to be very promising in terms of power savings [19], [20], [4], [7]. So we use these approximate adders in our experiments.…”

Section: A Application: Fir Filtermentioning

confidence: 99%

ErrorModelingLPAA.pdf

Dharmaraj¹,

Vasudevan²,

Chandrachoodan³

2019

Preprint

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Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we consider the problem of minimizing the power for a given accuracy, in a signal processing application with accurate adders replaced by low-power approximate adders. We first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits. To overcome this problem, we propose the use of parameterized error models for adders, with input static probabilities as parameters. The static probability computation in our work considers not just the functionality of the adder but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. This parameterized error model can be incorporated in any optimization framework. We demonstrate up to 6.5 dB improvement in the accuracy of noise power prediction when the proposed model is used to optimize an 8 × 8 DCT.

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“…As mentioned, in the literature, the distribution of the lower order bits is assumed to be uniform. Some justification for this assumption on primary inputs is included in [7]. In this paper, we derive an exact condition under which the lower order bits of a signal is uniformly distributed and check the validity of the assumption on primary input of an image processing application, where the intensity distribution of image pixels is very non-uniform.…”

Section: Introductionmentioning

confidence: 99%

“…A variety of approximate adders have been proposed in the literature, with different levels of trade-offs between accuracy and performance. These adders can be classified as low-latency [1] (and references therein) and low-power approximate adders [2]- [7]. In this paper, our focus is power optimized implementations of signal processing algorithms using low power approximate adders (LPAA).…”

Section: Introductionmentioning

confidence: 99%

ErrorModelingLPAA.pdf

Dharmaraj¹,

Vasudevan²,

Chandrachoodan³

2019

Preprint

Self Cite

View full text Add to dashboard Cite

Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we consider the problem of minimizing the power for a given accuracy, in a signal processing application with accurate adders replaced by low-power approximate adders. We first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits. To overcome this problem, we propose the use of parameterized error models for adders, with input static probabilities as parameters. The static probability computation in our work considers not just the functionality of the adder but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. This parameterized error model can be incorporated in any optimization framework. We demonstrate up to 6.5 dB improvement in the accuracy of noise power prediction when the proposed model is used to optimize an 8 × 8 DCT.

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“…These techniques can be classified based on computational accuracy, namely accurate, approximate, and accuracy-configurable design. The accurate design techniques exploit resource sharing and/or redundant logic elimination, whereas approximate design techniques identify and compute the sum of nonsignificant parts using approximate computing [2]. The accuracy-configurable designs are nothing but approximate designs with error detection and correction (EDC) logic to achieve the desired accuracy-performance trade-off.…”

Section: Introductionmentioning

confidence: 99%

A power and area efficient approximate carry skip adder for error resilient applications

Patel¹,

Garg²,

Kumar³

2020

Turk J Elec Eng & Comp Sci

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The compute-intensive multimedia applications on portable devices require power and area efficient arithmetic units. The adder is a prime building block of these arithmetic units and limits the overall performance. Therefore, this paper analyzes the logic operations of the state-of-the-art adders and presents a novel low complexity adder segment with new carry prediction logic by removing the redundant logic and sharing the common operations. Further, a new power and area efficient approximate carry skip (PAEA-CSK) adder is proposed using the novel adder segment. The effectiveness of the proposed PAEA-CSK adder is evaluated and compared over the existing adders by implementing them in VHDL and synthesizing using the Synopsys Design Compiler with the 65nm TSMC CMOS Library. The synthesis result shows that the proposed PAEA-CSK adder requires 27.28% and 18.03% less area and power, respectively, over the existing carry skip-based approximate adder with the same accuracy. Further, the Sobel edge detector (SED) embedded with the proposed adder improves PSNR by a minimum of 16.94 dB over the SED embedded with a nonzeroing bit-truncation adder.

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Optimizing power-accuracy trade-off in approximate adders

Cited by 11 publications

References 11 publications

ErrorModelingLPAA.pdf

ErrorModelingLPAA.pdf

ErrorModelingLPAA.pdf

A power and area efficient approximate carry skip adder for error resilient applications

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