35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.
DOI: 10.1109/micro.2002.1176261
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Optimizing pipelines for power and performance

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Cited by 91 publications
(78 citation statements)
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“…They argue that Et 2 provides the best balance between the two optimisation objectives for microprocessor design. Srinivasan et al reached the same conclusion, although for slightly different reasons [22].…”
Section: Related Workmentioning
confidence: 78%
“…They argue that Et 2 provides the best balance between the two optimisation objectives for microprocessor design. Srinivasan et al reached the same conclusion, although for slightly different reasons [22].…”
Section: Related Workmentioning
confidence: 78%
“…On the other hand, internal architectural counters used to compute the power consumed by cores count a number of relevant events and appropriately weight the counter values. For example, the total numbers of load/store instructions, arithmetic/logic instructions, floating-point operations, and retirement executions for each core are counted and summed up after being multiplied by appropriate weights [47]. The decision boundaries for an output measure are obtained as follows.…”
Section: B Detailed Resultsmentioning
confidence: 99%
“…To model the power overheads of deep pipelining, we employ the analytical models proposed by Srinivasan et al [38] to compute power-optimal pipeline depths. More details of this model and assumptions can be found in the original work [38]. Table 5 summarizes the impact of pipeline depth on total power, relative to a baseline pipeline that has a cycle time of 18 FO4.…”
Section: Conservative Timing Marginsmentioning
confidence: 99%