Optimizing memory performance for FPGA implementation of pagerank

Zhou, Shijie; Chelmis, Charalampos; Prasanna, Viktor K.

doi:10.1109/reconfig.2015.7393332

Cited by 38 publications

(17 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Comprehensibility [ZCP15] introduces a DRAM model and simulation of what would later become HitGraph. The simulation also generates the sequence of requests, but instead of simulating DRAM runtime, it assumes that every request results in a row buffer hit and models the performance along the cycles needed for processing the data and approximated pipelines stalls.…”

Section: Related Workmentioning

confidence: 99%

Exploring Memory Access Patterns for Graph Processing Accelerators

Dann¹,

Ritter²,

Fröning³

2020

Preprint

View full text Add to dashboard Cite

Recent trends in business and technology (e. g., machine learning, social network analysis) benefit from storing and processing growing amounts of graph-structured data in databases and data science platforms. FPGAs as accelerators for graph processing with a customizable memory hierarchy promise solving performance problems caused by inherent irregular memory access patterns on traditional hardware (e. g., CPU). However, developing such hardware accelerators is yet timeconsuming and difficult and benchmarking is non-standardized, hindering comprehension of the impact of memory access pattern changes and systematic engineering of graph processing accelerators.In this work, we propose a simulation environment for the analysis of graph processing accelerators based on simulating their memory access patterns. Further, we evaluate our approach on two state-ofthe-art FPGA graph processing accelerators and show reproducibility, comparablity, as well as the shortened development process by an example. Not implementing the cycle-accurate internal data flow on accelerator hardware like FPGAs significantly reduces the implementation time, increases the benchmark parameter transparency, and allows comparison of graph processing approaches.

show abstract

Section: Related Workmentioning

confidence: 99%

Exploring Memory Access Patterns for Graph Processing Accelerators

Dann¹,

Ritter²,

Fröning³

2020

Preprint

View full text Add to dashboard Cite

show abstract

“…Coalescing means combining multiple transfers of small items into fewer large ones. This method is widely adopted in graph accelerators [27,71,88,92,93] . For example, if the memory requests are adjacent in a vertex or edge list, these requests can be coalesced as one request for a block.…”

Section: Multiple I/o Portsmentioning

confidence: 99%

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

View full text Add to dashboard Cite

Graph is a well known data structure to represent the associated relationships in a variety of applications, e.g., data science and machine learning. Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred to as graph processing accelerators, are essential and emerging to provide the benefits significantly beyond those pure software solutions can offer. In this paper, we conduct a systematical survey regarding the design and implementation of graph processing accelerator. Specifically, we review the relevant techniques in three core components toward a graph processing accelerator: preprocessing, parallel graph computation and runtime scheduling. We also examine the benchmarks and results in existing studies for evaluating a graph processing accelerator. Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations. We finially present to discuss several challenges in details, and to further explore the opportunities for the future research.

show abstract

“…Algorithmic optimizations have been developed to improve the spatial locality of graph analytics kernels by reducing the number of cache misses [4], [26], [25], [6], but these approaches are typically application-dependent.…”

Section: Related Workmentioning

confidence: 99%

Performance Impact of Memory Channels on Sparse and Irregular Algorithms

Green

Fox

Young

et al. 2019

2019 IEEE/ACM 9th Workshop on Irregular Applications: Architectures and Algorithms (IA3)

View full text Add to dashboard Cite

Graph processing is typically considered to be a memory-bound rather than compute-bound problem. One common line of thought is that more available memory bandwidth corresponds to better graph processing performance. However, in this work we demonstrate that the key factor in the utilization of the memory system for graph algorithms is not necessarily the raw bandwidth or even the latency of memory requests. Instead, we show that performance is proportional to the number of memory channels available to handle small data transfers with limited spatial locality.Using several widely used graph frameworks, including Gunrock (on the GPU) and GAPBS & Ligra (for CPUs), we evaluate key graph analytics kernels using two unique memory hierarchies, DDR-based and HBM/MCDRAM. Our results show that the differences in the peak bandwidths of several Pascal-generation GPU memory subsystems aren't reflected in the performance of various analytics. Furthermore, our experiments on CPU and Xeon Phi systems demonstrate that the number of memory channels utilized can be a decisive factor in performance across several different applications. For CPU systems with smaller thread counts, the memory channels can be underutilized while systems with high thread counts can oversaturate the memory subsystem, which leads to limited performance. Finally, we model the potential performance improvements of adding more memory channels with narrower access widths than are found in current platforms, and we analyze performance trade-offs for the two most prominent types of memory accesses found in graph algorithms, streaming and random accesses.

show abstract

Optimizing memory performance for FPGA implementation of pagerank

Cited by 38 publications

References 11 publications

Exploring Memory Access Patterns for Graph Processing Accelerators

Exploring Memory Access Patterns for Graph Processing Accelerators

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Performance Impact of Memory Channels on Sparse and Irregular Algorithms

Contact Info

Product

Resources

About