Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer

A generic optimization methodology is presented for the design of drift region in lateral silicon‐on‐insulator (SOI) power devices. The methodology targets a drift region design with a low on resistance and a high reverse blocking capability. 2D drift diffusion technology computer aided design (TCAD) simulations are used to arrive at the principles of operation. As the drift region is a critical component of any lateral power device, the simulation domain is isolated to a generic n‐doped Si drift region, with symmetric top and bottom oxide () layers. A qualitative explanation based on charge sharing and the resulting electric field modulation is provided. The presence of oxide layers causes the drift region to be modulated such that it enables one to achieve a higher breakdown at a higher doping density. The main design parameters like drift doping, thickness, drift length, and oxide thickness are varied, and optimum values are identified for each. Finally, the extension of this optimization algorithm to other variants of lateral SOI devices is discussed.

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A Generic Methodology for Breakdown Voltage Optimization of Lateral Silicon‐On‐Insulator Power Devices

Kumar

Mudholkar

Quddus

2020

Physica Status Solidi (a)

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Improving Breakdown Behavior by Substrate Bias in a Novel Double Epi-layer Lateral Double Diffused MOS Transistor

Li¹,

Wang²,

Liu³

et al. 2012

Chinese Phys. Lett.

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A new lateral double diffused MOS (LDMOS) transistor with a double epitaxial layer formed by an n-type substrate and a p-type epitaxial layer is reported (DEL LDMOS). The mechanism of the improved breakdown characteristic is that the high electric field around the drain is reduced by substrate reverse bias, which causes the redistribution of the bulk electric field in the drift region, and the vertical blocking voltage is shared by the drain side and the source side. The numerical results indicate that the trade-off between breakdown voltage and on-resistance of the proposed device is improved greatly in comparison to that of the conventional LDMOS.

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Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer

Cited by 2 publications

References 9 publications

A Generic Methodology for Breakdown Voltage Optimization of Lateral Silicon‐On‐Insulator Power Devices

A Generic Methodology for Breakdown Voltage Optimization of Lateral Silicon‐On‐Insulator Power Devices

Improving Breakdown Behavior by Substrate Bias in a Novel Double Epi-layer Lateral Double Diffused MOS Transistor

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