Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond

Kikuda, S.; Miyata, Hiroshi; Mori, S.; Niiro, M.; Yarrada, M.

doi:10.1109/4.98971

Cited by 28 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The system may record some amount of fault history, and from this it would be very easy to detect that errors consistently occur in a particular column or set of columns. When this has been detected, the system could map out the column using spare resources [16], but such schemes are beyond the scope of this paper. Bank/Channel Failures: In the case of an entire bank failing, reading any row from that bank likely will result in garbage/random bit values, all zeros, or all ones.…”

Section: Identifying Coarse-grain Failuresmentioning

confidence: 99%

Resilient die-stacked DRAM caches

Sim

Loh²,

Sridharan

et al. 2013

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

Die-stacked DRAM can provide large amounts of in-package, high-bandwidth cache storage. For server and high-performance computing markets, however, such DRAM caches must also provide sufficient support for reliability and fault tolerance. While conventional off-chip memory provides ECC support by adding one or more extra chips, this may not be practical in a 3D stack. In this paper, we present a DRAM cache organization that uses error-correcting codes (ECCs), strong checksums (CRCs), and dirty data duplication to detect and correct a wide range of stacked DRAM failures, from traditional bit errors to large-scale row, column, bank, and channel failures. With only a modest performance degradation compared to a DRAM cache with no ECC support, our proposal can correct all single-bit failures, and 99.9993% of all row, column, and bank failures, providing more than a 54,000x improvement in the FIT rate of silent-data corruptions compared to basic SECDED ECC protection.

show abstract

Section: Identifying Coarse-grain Failuresmentioning

confidence: 99%

Resilient die-stacked DRAM caches

Sim

Loh²,

Sridharan

et al. 2013

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

show abstract

“…These types of systems include SRAM and DRAM memories [14], as well as systems designed using a set of bit planes and arithmeticlogic units (ALUs), assembled from ALU byte slices [19]. By far the most important use of bit-sliced BISR is in SRAM and DRAM circuits [17,9,22]. The bit-sliced BISR in memories significantly increases memory production profitability and is regularly used in essentially all modem DRAM designs.…”

Section: Related Workmentioning

confidence: 99%