Optimized Post-CMP and Pre-Epi Cleans to Enable Smooth and High Quality Epitaxial Strained Ge Growth on SiGe Strain Relaxed Buffers

Abstract

Further improving complementary metal oxide semiconductor (CMOS) performance beyond the 15 nm generation likely requires the use of high mobility materials like Ge for pMOS devices. However, Ge pMOS devices made in relaxed Ge do not outperform current state of the art uni-axially strained Si pMOS devices. This explains the current interest in compressively strained Ge like bi-axially strained Ge grown on top of SiGe Strain Relaxed Buffers. From a device integration point of view, the surface smoothness of the strained Ge layer is an important parameter which has so far not widely been reported in literature, in contrast to other parameters like the material quality (crystallinity) and the threading dislocation density. In this paper we report the post-CMP and pre-epi cleans which are required to obtain contamination free SiGe surfaces to enable defect free strained Ge growth without reoccurrence of the surface roughening. We will demonstrate the epitaxial growth of fully strained 20 nm thick Ge epitaxially grown on top of SiGe Strain Relaxed Buffers with 85% Ge with a surface roughness as low as 1.6 Å (as measured on areas of 10×10 µm2).

Catalyst Assisted Low Temperature Pre Epitaxial Cleaning for Si and SiGe Surfaces

“…Cleaning of Si at 550 o C and 600 o C (Figure 1.a) shows an increase in the etch rate with increasing temperature and an increase in the material removal rate with increasing etch time (Figure 1.b). PL measurements (data not shown in this paper) carried out on the cool cleaned samples capped with SiGe and Si indicated better quality of interface for the sample with 3nm of Si loss at 600 o C. For samples with <3nm of Si loss, we were not able to observe PL, indicating the presence of contaminants [8].…”