Proceedings of the 2002 International Workshop on System-Level Interconnect Prediction 2002
DOI: 10.1145/505348.505352
|View full text |Cite
|
Sign up to set email alerts
|

Optimized pin assignment for lower routing congestion after floorplanning phase

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2011
2011
2011
2011

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(1 citation statement)
references
References 5 publications
0
1
0
Order By: Relevance
“…An algorithm such as [ZS02] is used for subsequent pin assignment and to complete both the internal circuit and the global system-level routing.…”
Section: Pin Assignmentmentioning
confidence: 99%
“…An algorithm such as [ZS02] is used for subsequent pin assignment and to complete both the internal circuit and the global system-level routing.…”
Section: Pin Assignmentmentioning
confidence: 99%