Constraint-Based Layout-Driven Sizing of Analog Circuits

Habal, Husni; Graeb, Helmut

doi:10.1109/tcad.2011.2158732

Cited by 56 publications

(25 citation statements)

References 62 publications

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“…In Fig. 2.4, a traditional analog design flow with emphasis on circuit sizing is presented, versus the generalized layout-aware methodology proposed in [35]. Next, some state-of-the-art layout-aware synthesis tools and their different ways of extracting layout-parasitics are presented.…”

Section: Layout-aware Sizing Approachesmentioning

confidence: 99%

“…Recently, Habal et al [35] ruled out the use of templates given the few degrees of freedom they offer, investigating every possible layout for each device in the circuit using placement algorithm Plantage [2]. The layouts with the best geometric features are kept, and only the final placement selected based on aspect ratio, area and electrical performance is routed.…”

Section: Layout-aware Sizing Approachesmentioning

confidence: 99%

“…Ranjan [33] ALDAC [30] KOAN/ANAGRAM [27] ALADIN [23] LAYLA [28] Castro-Lopez [31] Zhang [25] Malavasi [29] Koda [16] Lin [18] ALG [24] Habal [35] Jingnan [20] Vancorenland [32] ALSYN [19] Legend:…”

Section: Template Optimizationmentioning

confidence: 99%

“…Most of the layout-aware solutions rely on procedural layout generations, which are known for their difficult reuse and lack of flexibility. The solution of [35] although avoids procedural generations, but at the expense of an increase in the computational time required to complete the automatic flow. The commercial tools presented, proved that only the approaches that allow for designers to integrate their knowledge into the synthesis process and offer control over the generation, found their way into the EDA market.…”

Section: Laygen IImentioning

confidence: 99%

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State of the Art on Analog Layout Automation

Martins¹,

Lourenço²,

Horta³

2012

Generating Analog IC Layouts With LAYGEN II

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In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. Yet, most of the layout design is still handmade, essentially because analog designers want to have total control over the different design options, and also, due to the fact that current fully automated generators of analog IC layouts produce solutions which are not yet competitive with the manually crafted ones. The state-of-the-art on analog layout automation that follows reveals that after many years of stagnation, electronic design automation (EDA) market is evolving, creating more efficient and complementary approaches to the existing tools. The chapter starts by addressing the placement problem in EDA, providing a brief overview of the most recent placement tools developed, followed by the presentation of the main references of automatic layout generation tools, and the recent advances in layout-aware analog synthesis approaches. Finally, the available commercial solutions for analog layout automation are outlined.

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Section: Layout-aware Sizing Approachesmentioning

confidence: 99%

Section: Layout-aware Sizing Approachesmentioning

confidence: 99%

Section: Template Optimizationmentioning

confidence: 99%

Section: Laygen IImentioning

confidence: 99%

See 2 more Smart Citations

State of the Art on Analog Layout Automation

Martins¹,

Lourenço²,

Horta³

2012

Generating Analog IC Layouts With LAYGEN II

View full text Add to dashboard Cite

show abstract

“…However, both complete layout generation and parasitic extraction are still time consuming tasks. This time cost appears either in the processing time, when using custom automatic layout generator plus layout extraction inside the sizing optimization loop [7], or in the design time of circuit specific procedural generators, that code the entire layout of a circuit in a tool, with parasitic estimation [6,8,9]. Fig.…”

Section: Introductionmentioning

confidence: 99%